Responding to application demand in a system that uses programmable logic components
Systems and methods provide an extensible, multi-stage, realtime application program processing load adaptive, manycore data processing architecture shared dynamically among instances of parallelized and pipelined application software programs, according to processing load variations of said programs and their tasks and instances, as well as contractual policies. The invented techniques provide, at the same time, both application software development productivity, through presenting for software a simple, virtual static view of the actually dynamically allocated and assigned processing hardware resources, together with high program runtime performance, through scalable pipelined and parallelized program execution with minimized overhead, as well as high resource efficiency, through adaptively optimized processing resource allocation.
1. An apparatus comprising:
a communication interface; and
hardware logic that implements a host logic, and a reconfigurable logic that implements an application logic, wherein the host logic encapsulates the application logic based on restricting the application logic's access to the communication interface;
wherein the host logic is configured to:
receive, from an entry stage processing system and via the communication interface, a first transaction to configure a part of the reconfigurable logic to implement the application logic;
based at least in part on receipt of the first transaction, configure the part of the reconfigurable logic to implement the application logic;
receive, from the entry stage processing system and via the communication interface, a second transaction targeted at the application logic; and
transmit the second transaction to the application logic; and
wherein the communication interface is accessible to the application logic only via the host logic.
2. The apparatus of claim 1 , wherein:
the communication interface is coupled with a physical interconnect; and
the host logic further comprises a translation layer configured to format transactions between the application logic and the physical interconnect.
3. The apparatus of claim 1 , wherein the host logic comprises:
a first interface to a shared peripheral accessible by the application logic; and
a translation layer configured to format transactions between the shared peripheral and the application logic.
4. The apparatus of claim 3 , wherein the shared peripheral comprises at least one of a configurable hardware platform (CHP), a memory device, or a storage device.
5. The apparatus of claim 3 , wherein the shared peripheral comprises a plurality of CHPs.
6. The apparatus of claim 1 , wherein the first transaction to configure the part of the reconfigurable logic to implement the application logic comprises a data packet containing an indication that the data packet is an input to the application logic.
7. The apparatus of claim 1 , further comprising the entry stage processing system, and wherein the entry stage processing system comprises a central processing unit configured to execute a first application task that directs the second transaction to the communication interface.
8. An apparatus comprising:
a communication interface; and
hardware logic that implements a host logic, and a reconfigurable logic that implements an application logic, wherein the host logic encapsulates the application logic based on restricting the application logic's access to the communication interface;
wherein the host logic comprises
a first interface to a shared peripheral accessible by the application logic, and
a translation layer configured to format transactions between the shared peripheral and the application logic, wherein the shared peripheral comprises a plurality of configurable hardware platforms (CHPs),
and wherein the host logic is configured to
receive, from an entry stage processing system and via the communication interface, a first transaction to configure a part of the reconfigurable logic to implement the application logic,
based at least in part on receipt of the first transaction, configure the part of the reconfigurable logic to implement the application logic,
receive, from the entry stage processing system and via the communication interface, a second transaction targeted at the application logic, and
transmit the second transaction to the application logic;
the apparatus further comprising a cross-connect through which the plurality of CHPs is reachable, wherein the first interface connects to the cross-connect.
9. An apparatus comprising:
a communication interface; and
hardware logic that implements a host logic, and a reconfigurable logic that implements an application logic, wherein the host logic encapsulates the application logic based on restricting the application logic's access to the communication interface;
wherein the host logic is configured to
receive, from an entry stage processing system and via the communication interface, a first transaction to configure a part of the reconfigurable logic to implement the application logic,
based at least in part on receipt of the first transaction, configure the part of the reconfigurable logic to implement the application logic,
receive, from the entry stage processing system and via the communication interface, a second transaction targeted at the application logic, and
transmit the second transaction to the application logic; and
wherein:
the reconfigurable logic comprises an array of reconfigurable processing cores; and
the part of the reconfigurable logic comprises a first reconfigurable processing core of the array of reconfigurable processing cores.
10. The apparatus of claim 9 , wherein the host logic is further configured to select, based at least in part on a prior configuration of the array of reconfigurable processing cores, the first reconfigurable processing core to reconfigure so as to implement the application logic.
11. The apparatus of claim 9 , wherein:
the application logic comprises a first application logic; and
the host logic is further configured to
receive, from the entry stage processing system and via the communication interface, a third transaction, and,
based on content of the third transaction, configure a second one of the array of reconfigurable processing cores to implement a second application logic.
12. The apparatus of claim 11 , wherein the host logic is further configured to:
receive, from the entry stage processing system and via the communication interface, a fourth transaction targeted at the second application logic; and
transmit the fourth transaction to the second application logic.
13. The apparatus of claim 12 , further comprising the entry stage processing system, wherein
the entry stage processing system is configured to host first and second application tasks to direct transactions respectively to the first and second application logic.
14. The apparatus of claim 13 , wherein the entry stage processing system is configured such that the first application task is in external communication with a first remote client, and the second application task is in external communication with a second remote client.
15. The apparatus of claim 9 , wherein the communication interface is accessible to the application logic only via the host logic.
16. An apparatus comprising:
a communication interface; and
hardware logic that implements a host logic, and a reconfigurable logic that implements an application logic, wherein the host logic encapsulates the application logic based on restricting the application logic's access to the communication interface;
wherein the host logic comprises receive logic and a controller and is configured to
receive, from an entry stage processing system and via the communication interface, a first transaction to configure a part of the reconfigurable logic to implement the application logic,
based at least in part on receipt of the first transaction, configure the part of the reconfigurable logic to implement the application logic,
receive, from the entry stage processing system and via the communication interface, a second transaction targeted at the application logic, and
transmit the second transaction to the application logic.
17. An apparatus comprising:
a communication interface; and
hardware logic that implements a host logic, and a reconfigurable logic that implements an application logic, wherein the host logic encapsulates the application logic based on restricting the application logic's access to the communication interface, wherein the reconfigurable logic is included in a configurable hardware platform;
wherein the host logic is configured to
receive, from an entry stage processing system and via the communication interface, a first transaction to configure a part of the reconfigurable logic to implement the application logic,
based at least in part on receipt of the first transaction, configure the part of the reconfigurable logic to implement the application logic,
receive, from the entry stage processing system and via the communication interface, a second transaction targeted at the application logic, and
transmit the second transaction to the application logic.
18. A method, comprising:
receiving, by hardware-implemented host logic and via a communication interface, a first transaction targeted at the host logic;
configuring, by the host logic and based on the first transaction, a region of a reconfigurable logic to implement an application logic, the host logic encapsulating the application logic based on restricting the application logic's access to the communication interface;
receiving, by the host logic and via the communication interface, a second transaction targeted at the application logic; and
transmitting, by the host logic to the application logic, the second transaction.
19. The method of claim 18 , further comprising:
formatting, by a translation logic of the host logic, the second transaction; and
transmitting, by the host logic to the application logic, the formatted second transaction.
20. The method of claim 19 , further comprising:
receiving, by the host logic from the application logic, a third transaction;
formatting, by the translation logic of the host logic, the third transaction based on specifications of a physical interconnect coupled with the host logic; and
transmitting, by the host logic to the physical interconnect, the formatted third transaction.