Memory device with dynamic processing level calibration

1. A system, comprising:

a memory array; and

a processing device coupled to the memory array, the processing device configured to iteratively adjust an active processing level used to process data stored in the memory array, wherein, for each iteration, the controller is configured to:

determine a first set of read results based on the active processing level,

determine a second set of read results based on using an offset processing level different than the active processing level, and

incrementally adjust the active processing level based on a comparison of the first and the second sets of read results.

2. The system of claim 1 , wherein the data is stored in the memory array according to a plurality of memory pages, and wherein the active processing level is adjusted per each of the plurality of memory pages.

3. The system of claim 2 , wherein one of the plurality of memory pages is randomly selected for iteratively adjusting the corresponding active processing level, wherein the one of the plurality of memory pages is selected from a fully-programmed memory block of the memory array.

4. The system of claim 1 , wherein the first and the second sets of read results are each error counts, and wherein the active processing level is a read level voltage.

5. The system of claim 4 , wherein:

the offset processing level is a first offset processing level;

the processing device is further configured to:

determine a third set of read results based on using a second offset processing level different than the active processing level and the first offset processing level; and

incrementally adjust the current processing level includes either increasing or decreasing the active processing level based on comparing (1) a first difference in error counts between the first and second sets of read results and (2) a second difference in error counts between the first and third sets of read results.

6. The system of claim 5 , wherein:

the first and the second offset processing levels are offset in opposite directions from the active processing level by an offset amount; and

incrementally increasing or decreasing the active processing level includes adjusting in a direction that corresponds to a lower change in error counts.

7. The system of claim 6 , wherein:

the first processing level is less than the active processing level by the offset amount;

the second processing level is greater than the active processing level by the offset amount; and

incrementally adjusting the active processing level includes decreasing the active processing level by an increment when the first difference in error counts is less than the second difference in error counts.

8. The system of claim 6 , wherein:

the first processing level is less than the active processing level by the offset amount;

the second processing level is greater than the active processing level by the offset amount; and

incrementally adjusting the active processing level includes increasing the active processing level by an increment when the second difference in error counts is less than the first difference in error counts.

9. The system of claim 1 , wherein the processing device is further configured to stop iterating when the comparison between the first and second sets of read results indicates that the active processing level is at or within a threshold range around an optimal level for minimizing an error characteristic.

10. The system of claim 9 , wherein the processing device is further configured to determine that the active processing level is at or near an optimal level based on comparing a previous change direction and a current change direction, wherein the previous change direction is calculated based on a previous processing level and the active processing level, and wherein the current change direction based on active processing level and the updated level.

11. A method of operating a system including a processing device and a memory array, the method comprising iteratively:

determining a first set of read results based on using an active processing level;

determining a second set of read results based on using an offset processing level; and

incrementally adjust the active processing level based on a comparison of the first set of read results and the second set of read results for each iteration.

12. The method of claim 11 , further comprising updating the offset processing level to a different value based on the comparison between the first and second sets of read results across one or more iterations.

13. The method of claim 11 , further comprising randomly selecting a memory page from a fully-programmed memory block of the memory array, wherein the active processing level for the selected memory page is iteratively adjusted.

14. The method of claim 11 , wherein the first and second sets of read results are each error counts, and wherein the active processing level is a read level voltage.

15. The method of claim 11 , wherein the offset processing level is a first offset processing level, the method further comprising:

determining a third set of read results using a second offset processing level different than the active processing level and the first offset processing level, and

wherein:

incrementally adjusting the active processing level includes increasing or decreasing the active processing level based on comparing (1) a first difference in error counts between the first and second sets of read results and (2) a second difference in error counts between the first and third sets of read results.

16. The method of claim 15 , wherein:

the first and the second offset processing levels are offset in opposite directions from the active processing level by an offset amount; and

incrementally increasing or decreasing the active processing level includes adjusting in a direction that corresponds to a lower change in error counts.

17. The method of claim 16 , wherein:

the first processing level is less than the active processing level by the offset amount;

the second processing level is greater than the active processing level by the offset amount; and

incrementally adjusting the active processing level includes (1) decreasing the active processing level by an increment when the first difference in error counts is less than the second difference in error counts or (2) increasing the active processing level by the increment when the second difference in error counts is less than the first difference in error counts.

18. The method of claim 11 , further comprising stopping the iteration when the comparison between the first and second sets of read results indicates that the active processing level is at or within a threshold range around an optimal level for minimizing an error characteristic.

19. The method of claim 18 , further comprising:

tracking a previous adjustment direction of either increasing or decreasing the active processing level for one or more iterations leading up to a current iteration;

calculating a current adjustment direction for the incremental adjustment for the current iteration; and

determining that the active processing level is at or within the offset range around the optimal level when the previous adjustment direction is different than the current adjustment direction.

20. A system, comprising:

a memory array including non-volatile memory cells arranged in memory pages; and

a processing device coupled to the memory array, the processing device configured to iteratively adjust a current read level voltage, wherein, for each iteration, the processing device is configured to:

determine a first set of read results corresponding to the active read level voltage,

determine a second set of read results based on using an offset read level voltage different from the active read level voltage, and

incrementally increase or decrease the active read level voltage for the memory page based on a comparison of the first and second sets of read results.