Differential subthreshold read of memory cell pair in a memory device
Systems, methods, and apparatus related to memory devices. In one approach, a differential read operation is performed on a memory cell pair. Bitlines or digit lines are used to select the memory cells. The read operation is performed in a subthreshold mode in which the memory cells of the pair do not threshold (e.g., do not switch or snap). A voltage on a wordline used to select the memory cell pair is ramped to increasing magnitudes of voltage while the bitline or digit line voltages are held fixed. One or more detectors are used to determine a difference in leakage currents of the two memory cells. A logic state is determined (e.g., using at least one detector) based on the difference in leakage currents. A feedback circuit reduces voltages applied to the bitlines or digit lines in order to avoid thresholding the cells. The voltage reduction by the feedback circuit is triggered when the reading of the memory cell pair is complete.
1 . An apparatus comprising:
a first detector coupled to a first memory cell, the first detector configured to output a first logic state;
a second detector coupled to a second memory cell, the second detector configured to output a second logic state; and
a feedback circuit configured to control, based on the first and second logic states, a voltage on a first digit line, and a voltage on a second digit line.
2 . The apparatus of claim 1 , wherein:
the feedback circuit comprises a comparator using the first and second logic states as inputs; and
the feedback circuit uses an output of the comparator to control the voltages on the first and second digit lines.
3 . The apparatus of claim 2 , wherein the comparator is a NAND logic gate.
4 . The apparatus of claim 1 , wherein the feedback circuit controls the voltages on the first and second digit lines to reduce a voltage applied to the first memory cell, and to reduce a voltage applied to the second memory cell.
5 . The apparatus of claim 1 , wherein the first and second memory cells correspond to storage of a single bit of data by a memory array.
6 . The apparatus of claim 1 , wherein the first detector is coupled to the first memory cell by the first digit line, and the second detector is coupled to the second memory cell by the second digit line.
7 . The apparatus of claim 1 , wherein an input to the first detector corresponds to a subthreshold current of the first memory cell, and an input to the second detector corresponds to a subthreshold current of the second memory cell.
8 . The apparatus of claim 1 , wherein:
the feedback circuit comprises a first transistor and a second transistor;
a current terminal of the first transistor is coupled to the first digit line;
a current terminal of the second transistor is coupled to the second digit line; and
an output of the feedback circuit is coupled to a gate terminal of the first transistor and a gate terminal of the second transistor.
9 . The apparatus of claim 1 , further comprising a first sense amplifier coupled between the first digit line and the first detector, and a second sense amplifier coupled between the second digit line and the second detector.
10 . The apparatus of claim 1 , further comprising a latch, wherein the first and second logic states are inputs to the latch, and an output of the latch corresponds to a bit of data stored in a memory array.
11 . The apparatus of claim 10 , wherein the latch is configured to latch the first and second logic states in response to an output of the feedback circuit.
12 . The apparatus of claim 11 , wherein the feedback circuit comprises a logic gate having the first and second logic states as inputs, and the output of the feedback circuit is an output of the logic gate.
13 . The apparatus of claim 1 , further comprising:
a first logic gate having the first and second logic states as inputs, the first logic gate having a first output; and
a second logic gate having a plurality of inputs, wherein the first output of the first logic gate is a first input to the second logic gate determined by reading the first and second memory cells as a first memory cell pair, and the second logic gate has other inputs determined by reading other memory cell pairs in a memory array, each of the first and other memory cell pairs corresponding to a respective bit stored in the memory array.
14 . The apparatus of claim 13 , further comprising a controller, wherein:
each of the plurality of inputs to the second logic gate corresponds to a respective bit in a codeword read from the memory array by the controller; and
an output of the second logic gate signals to the controller that all bits of the codeword have been read.
15 . A method comprising:
outputting a first logic state;
outputting a second logic state; and
controlling, by a feedback circuit based on the first and second logic states, a voltage on a first digit line, and a voltage on a second digit line;
wherein controlling the voltages on the first and second digit lines reduces a voltage.
16 . The method of claim 15 , wherein controlling the voltages on the first and second digit lines reduces a voltage applied to a first memory cell, and reduces a voltage applied to a second memory cell.
17 . The method of claim 16 , wherein the first and second memory cells correspond to storage of a single bit of data by a memory array.
18 . The method of claim 15 , wherein the first and second logic states are inputs to a latch, and an output of the latch corresponds to a bit of data stored in a memory array.
19 . The method of claim 18 , wherein the latch is configured to latch the first and second logic states in response to an output of a feedback circuit.
20 . The method of claim 19 , wherein the feedback circuit comprises a logic gate having the first and second logic states as inputs, and the output of the feedback circuit is an output of the logic gate.