Dc-dc converter control circuit
The present disclosure relates to semiconductor structures and, more particularly, to a dc-dc converter control circuit and methods of manufacture. The structure includes a dynamic pulse width modulation (PWM) circuit which converts a sense voltage to a variable current in response to a load current being above a predetermined threshold, and a ramp generator circuit which receives the variable current from the dynamic PWM circuit and dynamically adjusts a fixed base frequency of a PWM signal to a dynamic frequency of the PWM signal which corresponds with the load current.
1. A structure comprising:
a dynamic pulse width modulation (PWM) circuit which converts a sense voltage to a variable current in response to a load current being above a predetermined threshold, wherein the dynamic PWM circuit comprises a comparator that is enabled using an enable signal and the comparator outputs an enable variable current signal, the enable variable current signal and the converted sense voltage being utilized by a voltage-current converter to output the variable current; and
a ramp generator circuit which receives the variable current from the dynamic PWM circuit and dynamically adjusts a fixed base frequency of a PWM signal to a dynamic frequency of the PWM signal corresponding with the load current.
2. The structure of claim 1 , wherein the dynamic PWM circuit comprises the voltage-current converter which converts a load sensing voltage to the variable current.
3. The structure of claim 2 , wherein the comparator receives the load sensing voltage and a voltage equivalent of a minimum load current.
4. The structure of claim 3 , wherein the comparator receives the enable signal for enabling the comparator.
5. The structure of claim 2 , wherein the dynamic PWM circuit comprises a load current sense circuit which receives the sense voltage and outputs the load sensing voltage.
6. The structure of claim 1 , wherein the ramp generator circuit comprises a flip flop circuit which is reset in response to a ramp voltage being greater than a high voltage signal.
7. The structure of claim 6 , wherein the ramp generator circuit further comprises an NMOS transistor which is enabled in response to the flip flop circuit being reset.
8. The structure of claim 6 , wherein the flip flop circuit is set in response to the ramp voltage falling below a low voltage signal.
9. The structure of claim 1 , wherein the ramp generator circuit outputs the fixed base frequency in response to the load current being below the predetermined threshold.
10. The structure of claim 9 , wherein the variable current is zero in response to the load current being below the predetermined threshold.
11. The structure of claim 9 , wherein the fixed base frequency generates a fixed output voltage ripple in response to the load current being below the predetermined threshold.
12. A structure comprising:
a dynamic pulse width modulation (PWM) frequency control circuit comprising a voltage-current converter which receives a load sensing voltage and converts the load sensing voltage to a variable current, and a load current sense circuit which receives a sense voltage and outputs the load sensing voltage, the dynamic PWM frequency control circuit further comprising a comparator that is enabled using an enable signal and outputs an enable variable current signal to the voltage-current converter; and
a ramp generator circuit which receives the variable current from the dynamic PWM frequency control circuit and outputs a fixed base frequency in response to a load current being below a predetermined threshold, and dynamically adjusts the fixed base frequency of a PWM signal to a dynamic frequency of the PWM signal corresponding with the load current being above the predetermined threshold.
13. The structure of claim 12 , wherein the comparator receives the load sensing voltage and a voltage equivalent of a minimum load current.
14. The structure of claim 13 , wherein the comparator also receives the enable signal from a start-up detector for enabling the comparator.
15. The structure of claim 12 , wherein the ramp generator circuit comprises a flip flop circuit which is reset in response to a ramp voltage being greater than a high voltage signal.
16. The structure of claim 15 , wherein the ramp generator circuit further comprises an NMOS transistor which is enabled in response to the flip flop circuit being reset.
17. The structure of claim 15 , wherein the flip flop circuit is set in response to the ramp voltage falling below a low voltage signal.
18. The structure of claim 12 , wherein the variable current is zero in response to the load current being below the predetermined threshold.
19. The structure of claim 12 , wherein the fixed base frequency generates a fixed output voltage ripple in response to the load current being below the predetermined threshold.
20. A method comprising:
receiving an enable signal;
determining that a load current is above a predetermined threshold;
receiving the enable variable current signal and a sense voltage and converting the sense voltage and the enable variable current signal to a variable current in response to the load current being above the predetermined threshold, the enable variable current signal and the converted sense voltage being utilized by a voltage-current converter to output the variable current; and
dynamically adjusting a fixed base frequency of a PWM signal to a dynamic frequency of the PWM signal based on the variable current corresponding to the load current.