Integrated circuit device with low threshold voltage
A method of manufacturing a semiconductor device is provided. A substrate is provided. The substrate has a first region and a second region. An n-type work function layer is formed over the substrate in the first region but not in the second region. A p-type work function layer is formed over the n-type work function layer in the first region, and over the substrate in the second region. The p-type work function layer directly contacts the substrate in the second region. And the p-type work function layer includes a metal oxide.
1. A device, comprising:
a substrate including a semiconductor material;
a first gate structure in an n-type region of the substrate; and
a second gate structure in a p-type region of the substrate;
wherein:
the first gate structure includes a p-type work function layer deposited over an n-type work function layer, wherein the p-type work function layer includes both ruthenium oxide and unoxidized ruthenium;
the second gate structure includes the p-type work function layer deposited over the substrate;
the n-type work function layer includes Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, or TiAlN.
2. The device of claim 1 , wherein the second gate structure includes a capping layer over the p-type work function layer, and wherein the capping layer includes tantalum and nitrogen.
3. The device of claim 2 , wherein the p-type work function layer is in physical contact with the capping layer.
4. The device of claim 1 , wherein the second gate structure further includes a layer that is disposed below the p-type work function layer, and wherein the layer contains titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), tungsten carbonitride (WCN), titanium silicon nitride (TiSiN), or tantalum silicon nitride (TaSiN).
5. The device of claim 4 , wherein the layer is in direct contact with the p-type work function layer.
6. The device of claim 1 , wherein the first gate structure includes a plurality of semiconductor layers, and wherein the n-type work function layer is disposed over the plurality of semiconductor layers.
7. The device of claim 1 , wherein the p-type work function layer has a thickness between about 10 Å and about 15 Å.
8. The device of claim 1 , wherein a molar ratio between the unoxidized ruthenium and ruthenium oxide in the p-type work function layer is smaller than about 0.9:1.
9. The device of claim 1 , wherein the first gate structure, but not the second gate structure, further includes a protective layer that is disposed below the p-type work function layer.
10. The device of claim 9 , wherein the protective layer is disposed between the p-type work function layer and the n-type work function layer.
11. The device of claim 10 , wherein the protective layer is in physical contact with both the p-type work function layer and the n-type work function layer.
12. A device, comprising:
a first active region and a second active region each disposed over a substrate;
a first gate structure disposed over the first active region, wherein the first gate structure includes: a gate dielectric layer, a first layer disposed over the gate dielectric layer, an n-type work function layer disposed over the first layer, a second layer disposed over the n-type work function layer, and a p-type work function layer disposed over the second layer; and
a second gate structure disposed over the second active region, wherein the second gate structure includes: the gate dielectric layer, the first layer disposed over the gate dielectric layer, and the p-type work function layer disposed over the first layer;
wherein:
the n-type work function layer includes Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, or TiAlN; and
the p-type work function layer includes RuO 2 or IrO 2 .
13. The device of claim 12 , wherein:
the p-type work function layer includes RuO 2 and Ru; or
the p-type work function layer includes IrO 2 and Ir.
14. The device of claim 12 , wherein the p-type work function layer consists of RuO 2 or consists of IrO 2 .
15. The device of claim 12 , wherein:
in the first gate structure, the second layer is in physical contact with both the n-type work function layer and the p-type work function layer; and
in the second gate structure, the p-type work function layer is in physical contact with the first layer.
16. The device of claim 12 , wherein the first layer or the second layer contains TiN, TaN, WN, WCN, TiSiN, or TaSiN.
17. The device of claim 16 , wherein:
the second layer includes a first sub-layer and a second sub-layer;
the first sub-layer contains TiN, TaN, WN, WCN, TiSiN, or TaSiN; and
the second sub-layer contains Al 2 O 3 , SiO 2 , or GeO 2 .
18. A device, comprising:
an n-type transistor that includes:
a gate dielectric layer, a material layer disposed over the gate dielectric layer, an n-type work function layer disposed over and in physical contact with the material layer, a protective layer disposed over and in physical contact with the n-type work function layer, and a p-type work function layer disposed over and in physical contact with the protective layer; and
a p-type transistor that includes:
the gate dielectric layer, the material layer disposed over the gate dielectric layer, and the p-type work function layer disposed over and in physical contact with the material layer; and
wherein the p-type work function layer includes a metal oxide material.
19. The device of claim 18 , wherein the metal oxide material includes RuO 2 or IrO 2 .
20. The device of claim 18 , wherein the p-type transistor further includes a capping layer disposed over the p-type work function layer, and wherein the capping layer contains at least one of tantalum or nitrogen.