ELECTRONIC DEVICE WITH VARIABLE RESISTANCE LAYERS AND INSULATING LAYERS ALTERNATELY STACKED AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing an electronic device includes alternately forming first variable resistance layers and insulating layers, forming conductive pillars passing through the first variable resistance layers and the insulating layers, forming a slit passing through the first variable resistance layers and the insulating layers and extending in a first direction, forming openings by etching the first variable resistance layers exposed through the slit, and forming conductive layers in the respective openings.
1 . A method of manufacturing an electronic device including a semiconductor memory, the method comprising:
alternately forming first variable resistance layers and insulating layers;
forming conductive pillars passing through the first variable resistance layers and the insulating layers;
forming a slit passing through the first variable resistance layers and the insulating layers and extending in a first direction;
forming openings by etching the first variable resistance layers exposed through the slit; and
forming conductive layers in the respective openings.
2 . The method according to claim 1 , further comprising forming a slit insulating layer in the slit after forming the conductive layers.
3 . The method according to claim 1 , wherein the first variable resistance layers include amorphous chalcogenide.
4 . The method according to claim 1 , further comprising forming second variable resistance layers in the openings before forming the conductive layers.
5 . The method according to claim 4 , wherein the first variable resistance layers include amorphous chalcogenide, and the second variable resistance layers include phase-change material.
6 . The method according to claim 1 , wherein the first variable resistance layers are formed using a physical vapor deposition process.
7 . The method according to claim 1 , further comprising forming electrode layers in the openings and the slit, before the conductive layers are formed.
8 . The method according to claim 7 , further comprising forming second variable resistance layers in the openings and the slit where the electrode layers are formed,
wherein a sum of a thickness of each of the electrode layers and a thickness of each of the second variable resistance layers is smaller than a width of each of the openings in a second direction intersecting the first direction.
9 . The method according to claim 8 , further comprising removing portions of the electrode layers, the second variable resistance layers, and the conductive layers through the slit.
10 . The method according to claim 9 , wherein, after the removal is performed, remaining portions of the electrode layers and remaining portions of the second variable resistance layers each have a C-shaped cross-section.