Translation lookaside buffer consistency directory for use with virtually-indexed virtually-tagged first level data cache that holds page table permissions

1. A microprocessor, comprising:

a virtually-indexed and virtually-tagged cache having E entries, where E is the number of entries in the cache, wherein each cache entry is configured to hold:

a copy of a line of memory at a physical memory line address;

a tag of a virtual memory line address, wherein the virtual memory line address is translatable into the physical memory line address; and

permissions associated with a page of memory that encompasses the physical memory line address;

a directory having an E number of entries corresponding to the E number of cache entries, wherein the directory is physically arranged as R rows and C columns, where R is the number of rows in the directory and C is the number of columns in the directory, wherein R*C=E, wherein each directory entry is configured to hold:

a directory tag comprising one or more hashes of corresponding one or more portions of a page address, wherein the page address is a portion of the virtual memory line address whose tag is held in the cache entry corresponding to the directory entry; and

wherein in response to a translation lookaside buffer management instruction (TLBMI) that specifies a virtual address, the microprocessor is configured to:

generate a target tag comprising one or more hashes of corresponding one or more portions of a page address, wherein the page address is a portion of the virtual address specified by the TLBMI; and

for each row of the R rows of the directory:

for each directory entry of the C directory entries of the row:

make a comparison of the target tag with the directory tag of the directory entry; and

generate a match indictor based on the comparison; and

for each directory entry having a true match indictor, invalidate the corresponding cache entry.

2. The microprocessor of claim 1 ,

wherein the cache is logically arranged as S sets and W ways and has E=S*W entries, where S is the number of sets in the cache and W is the number of ways in the cache; and

wherein R is less than S, and C is greater than W.

3. The microprocessor of claim 1 ,

wherein each cache entry has a unique set and way that is specified by a set index and a way number; and

wherein each directory entry has a unique row and column that is specified by mutually exclusive first and second portions of a combination of the set index and way number of the corresponding cache entry.

4. The microprocessor of claim 1 ,

wherein the comparisons of the target tag with the directory tag of the directory entry are performed concurrently for all C directory entries of the row.

5. The microprocessor of claim 1 ,

wherein the directory tag and the target tag further comprise a hash of an address space identifier.

6. The microprocessor of claim 5 ,

wherein each directory entry is further configured to hold a global page indicator; and

wherein to generate the match indicator, if the global page indictor indicates the page of memory is a global page, the microprocessor ignores the comparison of the hash of the address space identifier.

7. The microprocessor of claim 5 ,

wherein to generate the match indicator, if the TLBMI specifies an address space identifier to be invalidated rather than a virtual address, the microprocessor ignores the comparison of the one or more hashes of the one or more portions of the page address.

8. The microprocessor of claim 1 ,

wherein the directory tag and the target tag further comprise a hash of a virtual machine identifier.

9. The microprocessor of claim 8 ,

wherein to generate the match indicator, if the microprocessor is not in a virtual machine mode, the microprocessor ignores the comparison of the hash of the virtual machine identifier.

10. The microprocessor of claim 1 ,

wherein the directory tag and the target tag further comprise a translation mode.

11. The microprocessor of claim 1 ,

wherein each directory entry is further configured to hold a page size; and

wherein to generate the match indicator, for different values of the page size, the microprocessor ignores the comparison of corresponding different zero or more of the one or more hashes of the one or more portions of the page address.

12. The microprocessor of claim 1 ,

wherein the permissions indicate whether the page of memory is readable and/or writeable.

13. The microprocessor of claim 1 ,

wherein the copy of the line of memory, the tag, and the permissions are written to the cache and the directory tag is written into the directory in response to a miss in the cache of the virtual memory line address.

14. The microprocessor of claim 1 , further comprising:

a load/store unit that executes load/store instructions that specify a load/store virtual address; and

wherein the load/store unit is configured to complete execution of the load/store instruction only when the load/store virtual address hits in an entry of the cache and receives the permissions held in the hit upon entry of the cache.

15. A method, comprising:

in a microprocessor comprising:

a virtually-indexed and virtually-tagged cache having E entries, where E is the number of entries in the cache, wherein each cache entry is configured to hold:

a copy of a line of memory at a physical memory line address;

a tag of a virtual memory line address, wherein the virtual memory line address is translatable into the physical memory line address; and

permissions associated with a page of memory that encompasses the physical memory line address; and

a directory having an E number of entries corresponding to the E number of cache entries, wherein the directory is physically arranged as R rows and C columns, where R is the number of rows in the directory and C is the number of columns in the directory, wherein R*C=E, wherein each directory entry is configured to hold:

a directory tag comprising one or more hashes of corresponding one or more portions of a page address, wherein the page address is a portion of the virtual memory line address whose tag is held in the cache entry corresponding to the directory entry;

in response to a translation lookaside buffer management instruction (TLBMI) that specifies a virtual address:

generating a target tag comprising one or more hashes of corresponding one or more portions of a page address, wherein the page address is a portion of the virtual address specified by the TLBMI; and

for each row of the R rows of the directory:

for each directory entry of the C directory entries of the row:

making a comparison of the target tag with the directory tag of the directory entry; and

generating a match indictor based on the comparison; and

for each directory entry having a true match indictor:

invalidating the corresponding cache entry.

16. The method of claim 15 ,

wherein the cache is logically arranged as S sets and W ways and has E=S*W entries, where S is the number of sets in the cache and W is the number of ways in the cache; and

wherein R is less than S, and C is greater than W.

17. The method of claim 15 ,

wherein each cache entry has a unique set and way that is specified by a set index and a way number; and

wherein each directory entry has a unique row and column that is specified by mutually exclusive first and second portions of a combination of the set index and way number of the corresponding cache entry.

18. The method of claim 15 ,

wherein the comparisons of the target tag with the directory tag of the directory entry are performed concurrently for all C directory entries of the row.

19. The method of claim 15 ,

wherein the directory tag and the target tag further comprise a hash of an address space identifier.

20. The method of claim 19 ,

wherein each directory entry is further configured to hold a global page indicator; and

wherein said generating the match indicator comprises:

if the global page indictor indicates the page of memory is a global page, ignoring the comparison of the hash of the address space identifier.

21. The method of claim 19 ,

wherein said generating the match indicator comprises:

if the TLBMI specifies an address space identifier to be invalidated rather than a virtual address, ignoring the comparison of the one or more hashes of the one or more portions of the page address.

22. The method of claim 15 ,

wherein the directory tag and the target tag further comprise a hash of a virtual machine identifier.

23. The method of claim 22 ,

wherein said generating the match indicator comprises:

if the microprocessor is not in a virtual machine mode, ignoring the comparison of the hash of the virtual machine identifier.

24. The method of claim 15 ,

wherein the directory tag and the target tag further comprise a translation mode.

25. The method of claim 15 ,

wherein each directory entry is further configured to hold a page size; and

wherein said generating the match indicator comprises:

for different values of the page size, ignoring the comparison of corresponding different zero or more of the one or more hashes of the one or more portions of the page address.

26. The method of claim 15 ,

wherein the permissions indicate whether the page of memory is readable and/or writeable.

27. The method of claim 15 , further comprising:

writing the copy of the line of memory, the tag, and the permissions to the cache and writing the directory tag into the directory in response to a miss in the cache of the virtual memory line address.

28. The method of claim 15 ,

wherein the microprocessor further includes a load/store unit that executes load/store instructions that specify a load/store virtual address; and

wherein the load/store unit is configured to complete execution of the load/store instruction only when the load/store virtual address hits in an entry of the cache and receives the permissions held in the hit upon entry of the cache.

29. A non-transitory computer-readable medium having instructions stored thereon that are capable of causing or configuring a microprocessor comprising:

a virtually-indexed and virtually-tagged cache having E entries, where E is the number of entries in the cache, wherein each cache entry is configured to hold:

a copy of a line of memory at a physical memory line address;

a tag of a virtual memory line address, wherein the virtual memory line address is translatable into the physical memory line address; and

permissions associated with a page of memory that encompasses the physical memory line address;

a directory having an E number of entries corresponding to the E number of cache entries, wherein the directory is physically arranged as R rows and C columns, where R is the number of rows in the directory and C is the number of columns in the directory, wherein R*C=E, wherein each directory entry is configured to hold:

a directory tag comprising one or more hashes of corresponding one or more portions of a page address, wherein the page address is a portion of the virtual memory line address whose tag is held in the cache entry corresponding to the directory entry; and

wherein in response to a translation lookaside buffer management instruction (TLBMI) that specifies a virtual address, the microprocessor is configured to:

generate a target tag comprising one or more hashes of corresponding one or more portions of a page address, wherein the page address is a portion of the virtual address specified by the TLBMI; and

for each row of the R rows of the directory:

for each directory entry of the C directory entries of the row:

make a comparison of the target tag with the directory tag of the directory entry; and

generate a match indictor based on the comparison; and

for each directory entry having a true match indictor, invalidate the corresponding cache entry.