Programming delay scheme for a memory sub-system based on memory reliability
A system includes a memory device and a processing device operatively coupled to the memory device. The processing device is to receive a programming command with respect to a set of memory cells coupled to one or more wordlines of the memory device. The processing device is further to determine a value of a metric reflecting reliability of a subset of the set of memory cells. The processing device is further to determine a delay based on the value of the metric. The processing device is further to perform a programming operation with respect to the subset of memory cells. The programming operation includes the delay between a first pass of the programming operation and a second pass of the programming operation.
1. A system comprising:
a memory device; and
a processing device operatively coupled with the memory device, the processing device to:
receive a programming command with respect to a set of memory cells coupled to one or more wordlines of the memory device;
determine a value of a metric reflecting reliability of a subset of the set of memory cells;
determine a delay based on the value of the metric reflecting reliability, wherein the delay is determined from one or more values of a look-up table that correlates the value of the metric reflecting reliability with a predetermined delay duration; and
perform a programming operation with respect to the subset, wherein the programming operation comprises the delay between a first pass of the programming operation and a second pass of the programming operation.
2. The system of claim 1 , wherein the processing device is further to:
determine a program sequence of the programming operation, wherein the program sequence comprises:
a first first pass of the programming operation to be performed on a first set of sub-blocks coupled to a first wordline of the one or more wordlines of the memory device;
a second first pass of the programming operation to be performed on a second set of sub-blocks coupled to a second wordline of the one or more wordlines of the memory device; and
a first second pass of the programming operation to be performed on the first set of sub-blocks coupled to the first wordline.
3. The system of claim 1 , wherein the processing device is further to:
determine, based on the value of the metric reflecting reliability, a number of wordlines in a wordline group corresponding to the subset of the set of memory cells.
4. The system of claim 1 , wherein the delay is determined further based on a threshold value of the metric reflecting reliability.
5. The system of claim 1 , wherein the programming operation uses one of a source to drain program sequence or a drain to source program sequence.
6. The system of claim 1 , wherein the processing device is further to:
determine that the value of the metric reflecting reliability falls below a memory reliability threshold of the subset of the set of memory cells.
7. The system of claim 1 , wherein the delay reflects a difference between reliability of the subset of the set of memory cells and a predetermined memory reliability threshold.
8. A method comprising:
receiving a programming command with respect to a set of memory cells coupled to one or more wordlines of a memory device;
determining a value of a metric reflecting reliability of the set of memory cells;
determining a delay based on the value of the metric, wherein the delay is determined from one or more values of a look-up table that correlates the value of the metric reflecting reliability with a predetermined delay duration; and
performing a programming operation with respect to the set of memory cells, wherein the programming operation comprises the delay between a first pass of the programming operation and a second pass of the programming operation.
9. The method of claim 8 further comprising:
determining a program sequence of the programming operation, wherein the program sequence comprises:
a first first pass of the programming operation to be performed on a first set of sub-blocks coupled to a first wordline of the one or more wordlines of the memory device;
a second first pass of the programming operation to be performed on a second set of sub-blocks coupled to a second wordline of the one or more wordlines of the memory device; and
a first second pass of the programming operation to be performed on the first set of sub-blocks coupled to the first wordline.
10. The method of claim 8 further comprising:
determining, based on the value of the metric reflecting reliability, a number of wordlines in a wordline group corresponding to the set of memory cells.
11. The method of claim 8 , wherein the delay is determined further based on a threshold value of the metric reflecting reliability.
12. The method of claim 8 , wherein the programming operation uses one of a source to drain program sequence or a drain to source program sequence.
13. The method of claim 8 further comprising:
determining that the value of the metric reflecting reliability falls below a memory reliability threshold of the set of memory cells.
14. The method of claim 8 , wherein the delay reflects a difference between the reliability of the set of memory cells and a predetermined memory reliability threshold.
15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
receive a programming command with respect to a set of memory cells coupled to one or more wordlines of a memory device;
determine a value of a metric reflecting reliability of a subset of the set of memory cells;
determine a delay based on the value of the metric reflecting reliability, wherein the delay is determined from one or more values of a look-up table that correlates the value of the metric reflecting reliability with a predetermined delay duration; and
perform a programming operation with respect to the subset, wherein the programming operation comprises the delay between a first pass of the programming operation and a second pass of the programming operation.
16. The non-transitory computer-readable storage medium of claim 15 , wherein the processing device is further to:
determine a program sequence of the programming operation, wherein the program sequence comprises:
a first first pass of the programming operation to be performed on a first set of sub-blocks coupled to a first wordline of the one or more wordlines of the memory device;
a second first pass of the programming operation to be performed on a second set of sub-blocks coupled to a second wordline of the one or more wordlines of the memory device; and
a first second pass of the programming operation to be performed on the first set of sub-blocks coupled to the first wordline.
17. The non-transitory computer-readable storage medium of claim 15 , wherein the processing device is further to:
determine, based on the value of the metric reflecting reliability, a number of wordlines in a wordline group corresponding to the subset of the set of memory cells.
18. The non-transitory computer-readable storage medium of claim 15 , wherein the delay is determined further based on a threshold value of the metric reflecting reliability.
19. The non-transitory computer-readable storage medium of claim 15 , wherein the programming operation uses one of a source to drain program sequence or a drain to source program sequence.
20. The non-transitory computer-readable storage medium of claim 15 , wherein the processing device is further to:
determine that the value of the metric reflecting reliability falls below a memory reliability threshold of the subset of the set of memory cells.