Silicon carbide semiconductor device
A silicon carbide semiconductor device includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. A gate trench is provided in the first main surface. The gate trench is defined by side surfaces and a bottom surface. The side surfaces penetrate the source region and the body region to reach the drift region. The bottom surface connects to the side surfaces. The gate trench extends in a first direction parallel to the first main surface. The silicon carbide substrate further includes an electric field relaxation region that is the second conductive type, the electric field relaxation region being provided between the bottom surface and the second main surface and extending in the first direction, and a connection region that is the second conductive type, the connection region electrically connecting a contact region to the electric field relaxation region. In a plan view in a direction normal to the first main surface, the gate trench and the electric field relaxation region are disposed on a virtual line that extends in the first direction, and the connection region is in contact with the electric field relaxation region on the virtual line.
1. A silicon carbide semiconductor device comprising a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate including:
a drift region that is a first conductive type;
a body region that is a second conductive type different from the first conductive type, the body region being provided on the drift region;
a source region that is the first conductive type, the source region being provided on the body region to be separated from the drift region, and
a contact region that is the second conductive type, the contact region being provided on the body region,
wherein a gate trench is provided in the first main surface, the gate trench being defined by side surfaces and a bottom surface, the side surfaces penetrating the source region and the body region to reach the drift region, the bottom surface connecting to the side surfaces, and the gate trench extending in a first direction parallel to the first main surface,
the silicon carbide semiconductor device further comprising a source electrode connected to the source region and the contact region, the silicon carbide substrate further including:
an electric field relaxation region that is the second conductive type, the electric field relaxation region being provided between the bottom surface and the second main surface and extending in the first direction; and
a connection region that is the second conductive type, the connection region electrically connecting the contact region to the electric field relaxation region,
wherein, in a plan view in a direction normal to the first main surface, the gate trench and the electric field relaxation region are disposed on a virtual line that extends in the first direction, and the connection region is in contact with the electric field relaxation region on the virtual line.
2. The silicon carbide semiconductor device as claimed in claim 1 ,
wherein a plurality of said gate trenches are provided to overlap the virtual line at constant intervals, and
wherein the connection region is provided between adjacent gate trenches among the plurality of gate trenches, the adjacent gate trenches being adjacent in the first direction in the plan view.
3. The silicon carbide semiconductor device as claimed in claim 2 , further comprising:
a gate insulating film that is in contact with the side surfaces and the bottom surface;
a gate electrode provided on the gate insulating film to sandwich the gate insulating film between the gate electrode and the silicon carbide substrate; and
an interlayer insulating film provided to cover the gate electrode,
wherein, in the plan view in the direction perpendicular to the first direction, the contact region has a first region and a second region, the first region being provided to be spaced away from the interlayer insulating film in a second direction perpendicular to the first direction, and the second region being provided between the adjacent gate trenches,
wherein the source electrode is connected to the first region, and
wherein a first dimension of the first region in the first direction is greater than a second dimension of the second region in the first direction.
4. The silicon carbide semiconductor device as claimed in claim 3 , wherein the first dimension is one or greater and six or less times the second dimension.
5. The silicon carbide semiconductor device as claimed in claim 3 ,
wherein the source region and the first region are alternately provided in the first direction, and
wherein the first dimension is greater than a third dimension of the source region in the first direction.
6. The silicon carbide semiconductor device as claimed in claim 3 ,
wherein the source region and the first region are alternately provided in the first direction, and
wherein the first dimension is 0.2 or greater and 0.6 or less times a sum of the first dimension and a third dimension of the source region in the first direction.
7. The silicon carbide semiconductor device as claimed in claim 3 ,
wherein the second region is exposed from the interlayer insulating film, and
wherein the source electrode is also connected to the second region.
8. The silicon carbide semiconductor device as claimed in claim 3 , wherein the first region of the contact region is provided on each side of the gate trench in the second direction.
9. The silicon carbide semiconductor device as claimed in claim 3 , wherein the first region of the contact region is provided on only one side of the gate trench in the second direction.
10. The silicon carbide semiconductor device as claimed in claim 1 , wherein a first effective concentration of a second conductive type impurity in the contact region is higher than a second effective concentration of a second conductive type impurity in the connection region.
11. The silicon carbide semiconductor device as claimed in claim 1 , wherein the side surfaces of the gate trench include a {0-33-8} plane.