IP Library › Granted Patent US 12,349,385
Granted Patent B2
US 12,349,385 · App. 17/756,004 · Granted Jul 1, 2025

Semiconductor device, electric circuit, and wireless communication apparatus

Inventor: Masashi Yanagita (Kanagawa, JP)
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
H10D30/47H10D30/015H10D62/151H10D62/824H10D62/8503
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Quick Facts
Patent No.
US 12,349,385
App. No.
17/756,004
Granted
Jul 1, 2025
Kind
B2
Abstract

A semiconductor device includes a channel layer, a barrier layer, and at least one contact layer. The channel layer includes a GaN-based material. The barrier layer includes an AlInN-based material in which a composition ratio of In is higher than 18%, and is provided on the channel layer. The at least one contact layer includes a conductive-type semiconductor material and is provided to penetrate the barrier layer and reach the channel layer.

Claims (46)

1. A semiconductor device, comprising:

a channel layer including a GaN-based material;

a barrier layer including an AlInN-based material in which a composition ratio of In is higher than 18%, wherein the barrier layer is on the channel layer; and

at least one contact layer including a conductive-type semiconductor material, wherein

the at least one contact layer is positioned through the barrier layer and in contact with the channel layer,

the at least one contact layer is in a region at a depth within 100 nm from a first surface of the barrier layer that is on an opposite side to a second surface of the barrier layer, and

the second surface of the barrier layer is in contact with the channel layer.

2. The semiconductor device according to claim 1 , wherein

the at least one contact layer includes a first contact layer and a second contact layer,

each of the first contact layer and the second contact layer is on a respective side of a gate electrode such that the gate electrode is between the first contact layer and the second contact layer,

the gate electrode is on the barrier layer, and

a dielectric film is between the gate electrode and the barrier layer.

3. The semiconductor device according to claim 2 , wherein the first contact layer is electrically coupled to a source electrode, and the second contact layer is electrically coupled to a drain electrode.

4. The semiconductor device according to claim 3 , wherein sheet resistance between the gate electrode and the source electrode, or between the gate electrode and the drain electrode, is one of 280 Ω/square or less.

5. The semiconductor device according to claim 3 , wherein a sheet carrier concentration between the gate electrode and the source electrode, or between the gate electrode and the drain electrode, is one of 1.3×10 13 cm 2 or higher.

6. The semiconductor device according to claim 1 , wherein contact resistance between the contact layer and a channel provided at an interface between the channel layer and the barrier layer is one of 0.1 Ω·mm or less.

7. The semiconductor device according to claim 1 , wherein the contact layer includes an n-type GaN-based material as the conductive-type semiconductor material.

8. The semiconductor device according to claim 7 , wherein the n-type GaN-based material includes one of 2×10 20 cm −3 or more of an n-type impurity.

9. The semiconductor device according to claim 1 , wherein a carrier concentration of the contact layer is one of 8×10 19 cm −3 or higher.

10. The semiconductor device according to claim 1 , wherein the composition ratio of In in the barrier layer is one of 20% or lower.

11. The semiconductor device according to claim 1 , wherein the contact layer is in contact with an interface between the channel layer and the barrier layer.

12. A semiconductor device, comprising:

a channel layer including a GaN-based material;

a spacer layer including an AlN-based material, wherein the spacer layer is on the channel layer;

a barrier layer including an AlInN-based material in which a composition ratio of In is higher than 18%, wherein the barrier layer is on the spacer layer; and

at least one contact layer including a conductive-type semiconductor material, wherein

the at least one contact layer is positioned through the barrier layer and the spacer layer, and in contact with the channel layer,

the at least one contact layer is in a region at a depth within 100 nm from a first surface of the barrier layer that is on an opposite side to a second surface of the barrier layer, and

the second surface of the barrier layer is in contact with the spacer layer.

13. The semiconductor device according to claim 12 , wherein the contact layer is in contact with an interface between the channel layer and the spacer layer.

14. An electric circuit, comprising:

a semiconductor device that includes:

a channel layer including a GaN-based material;

a barrier layer including an AlInN-based material in which a composition ratio of In is higher than 18%, wherein the barrier layer is on the channel layer; and

at least one contact layer including a conductive-type semiconductor material, wherein

the at least one contact layer is positioned through the barrier layer and in contact with the channel layer,

the at least one contact layer is in a region at a depth within 100 nm from a first surface of the barrier layer that is on an opposite side to a second surface of the barrier layer, and

the second surface of the barrier layer is in contact with the channel laver.

15. A wireless communication apparatus, comprising:

a semiconductor device including

a channel layer including a GaN-based material;

a barrier layer including an AlInN-based material in which a composition ratio of In is higher than 18%, wherein the barrier layer is on the channel layer; and

at least one contact layer including a conductive-type semiconductor material, wherein

the at least one contact layer is positioned through the barrier layer and in contact with the channel layer,

the at least one contact layer is in a region at a depth within 100 nm from a first surface of the barrier layer that is on an opposite side to a second surface of the barrier laver, and

the second surface of the barrier layer is in contact with the channel layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: YANAGITA, MASASHI
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 060803/0174 →
Priority Claims (1)
JP 2019-210559 · Nov 21, 2019 · national
Continuity (1)
Related Publication 20220416065A1 · Dec 29, 2022
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