Memory built-in self-test with automated reference trim feedback for memory sensing
This application discloses a memory built-in self-test system to prompt a memory device to sense values of stored data using a reference trim during memory read operations. The memory built-in self-test system can automatically set the reference trim for the memory device. The memory built-in self-test system includes a memory built-in self-test controller to prompt the memory device to perform the memory read operations with different test values for the reference trim. The memory built-in self-test system also includes a trim feedback circuit to determine when the memory device fails to correctly sense the values of the stored data using the test values for the reference trim, and set the reference trim for the memory device based, at least in part, on the failures of the memory device to correctly sense the stored data.
1. A system comprising:
a memory device configured to sense values of stored data using a reference trim during memory read operations; and
a memory built-in self-test system configured to prompt the memory device to perform a plurality of the memory read operations with multiple test values for the reference trim, determine when the memory device fails to correctly sense the values of the stored data using the test values for the reference trim by comparing the sensed values of the stored data against an expected value to identify the failures, accumulate the failures of the memory device to correctly sense the stored data, compare the accumulated failures to a threshold failure quantity corresponding to an accumulation of memory device failures when using a boundary test value for the reference trim, and set bits of the reference trim for the memory device based, at least in part, on comparisons of the accumulated failures to the threshold failure quantity.
2. The system of claim 1 , wherein the memory built-in self-test system is configured to iteratively select the test values for the reference trim using a binary search based, at least in part, on the failures of the memory device to correctly sense the stored data.
3. The system of claim 1 , wherein the test values correspond to at least one of resistance values, current values, or voltage values.
4. The system of claim 1 , wherein the memory device is a Magnetoresistive Random Access Memory (MRAM) device.
5. A method comprising:
sensing, by a memory device, values of stored data using multiple test values for a reference trim during memory read operations,
determining, by a memory built-in self-test system, when the memory device fails to correctly sense the values of the stored data using the test values for the reference trim by comparing the sensed values of the stored data against an expected value to identify the failures;
accumulating, by the memory built-in self-test system, the failures of the memory device to correctly sense the stored data;
comparing, by the memory built-in self-test system, the accumulated failures to a threshold failure quantity corresponding to an accumulation of memory device failures when using a boundary test value for the reference trim; and
setting, by the memory built-in self-test system, bits of the reference trim based, at least in part, on the;
setting, by the memory built-in self-test system, bits of the reference trim for the memory device based, at least in part, on the comparisons of the accumulated failures to the threshold failure quantity.
6. The method of claim 5 , further comprising iteratively selecting, by the memory built-in self-test system, the test values for the reference trim using a binary search based, at least in part, on the failures of the memory device to correctly sense the stored data.
7. The method of claim 5 , wherein the test values correspond to at least one of resistance values, current values, or voltage values.
8. The method of claim 5 , wherein the memory device is a Magnetoresistive Random Access Memory (MRAM) device.
9. An apparatus comprising:
a memory built-in self-test controller configured to prompt a memory device to perform memory read operations with multiple test values for a reference trim, wherein the memory device is configured to sense values of stored data using the reference trim during the memory read operations; and
a trim feedback circuit configured to determine when the memory device fails to correctly sense the values of the stored data using the test values for the reference trim by comparing the sensed values of the stored data against an expected value to identify the failures, accumulate the failures of the memory device to correctly sense the stored data, compare the accumulated failures to a threshold failure Quantity corresponding to an accumulation of memory device failures when using a boundary test value for the reference trim, and set bits of the reference trim for the memory device based, at least in part, on the failures of the memory device to correctly sense the stored data.
10. The apparatus of claim 9 , wherein the trim feedback circuit is configured to iteratively select the test values for the reference trim using a binary search based, at least in part, on the failures of the memory device to correctly sense the stored data.
11. The apparatus of claim 9 , wherein the test values correspond to at least one of resistance values, current values, or voltage values.