IP Library Granted Patent US 11,853,150
Granted Patent B2
US 11,853,150 · App. 17/762,213 · Granted Dec 26, 2023

Method and device for detecting memory downgrade error

Inventors: Pengfang Luo (Suzhou, CN); Leijun Hu (Suzhou, CN)
Assignee: Inspur Suzhou Intelligent Technology Co., Ltd.
G06F11/079G06F11/073
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Quick Facts
Patent No.
US 11,853,150
App. No.
17/762,213
Granted
Dec 26, 2023
Kind
B2
Abstract

A method and device for detecting a memory downgrade error. The method comprises: capturing and analyzing a memory error by means of an operating system (OS); sending a memory downgrade error log to a management chip BMC on a server motherboard according to the analysis result; and after the BMC receives log information, detecting and locating an uncorrectable memory inspection error on the basis of an algorithm.

Claims (11)

1. A method for detecting a memory downgrade error, comprising:

setting a memory error of a central processing unit (CPU) to be such that a correctable machine check interrupt (CMCI) is triggered every time a correctable error occurs, wherein intercepting and parsing a memory error is performed by the CMCI of an operating system (OS), when a system management interrupt (SMI) of the OS is disabled;

sending a memory downgrade error log to a baseboard management controller (BMC) on a server motherboard according to a parsing result; and

detecting and locating an uncorrectable memory inspection error according to a memory conversion algorithm after the BMC receives log information.

2. The method for detecting the memory downgrade error according to claim 1 , wherein, before intercepting and parsing the memory error by means of the operating system, the method comprises:

adding a function for processing a memory downgrade error in a correctable machine check interrupt (CMCI) code in a kernel of the operating system; and

starting an enhanced machine check architecture generation 2 (EMCA2) in a basic input output system (BIOS) code, and setting an error generation interrupt type related to a memory to be CMCI.

3. The method for detecting the memory downgrade error according to claim 1 , wherein, the intercepting and parsing the memory error by means of the operating system comprises:

performing data parsing on a machine check bank (MC bank) during the processing of the CMCI; acquiring a specific fault memory address and an error type by means of the MC bank each time the operating system receives the CMCI after the operating system of a machine is boosted; and sending the log information to the BMC in the case that the error type is a degradation error.

4. The method for detecting the memory downgrade error according to claim 3 , wherein, the detecting and locating the uncorrectable memory inspection error according to the algorithm after the BMC receives log information comprises:

obtaining a memory bank position by means of a memory conversion algorithm according to a memory address after the BMC receives the log information.

Assignments (2)
LICENSE Recorded Jun 30, 2026
From: IEIT SYSTEMS CO., LTD
To: AIVRES SYSTEMS INC.
Reel/Frame 075857/0939 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2022
From: LUO, PENGFANG; HU, LEIJUN
To: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
Reel/Frame 059712/0953 →
Priority Claims (1)
CN 201910932646.6 · Sep 29, 2019 · national
Continuity (1)
Related Publication 20220342740A1 · Oct 27, 2022