IP Library Granted Patent US 11,949,223
Granted Patent B2
US 11,949,223 · App. 17/763,019 · Granted Apr 2, 2024

Direct-current power supply parallel-machine input reverse connection prevention circuit and server system

Inventor: Pengfei Gao (Suzhou, CN)
Assignee: Inspur Suzhou Intelligent Technology Co., Ltd.
H02H11/003H02J7/0034
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Quick Facts
Patent No.
US 11,949,223
App. No.
17/763,019
Granted
Apr 2, 2024
Kind
B2
Abstract

A direct-current power supply parallel-machine input reverse connection prevention circuit and a server. The circuit comprises a first switch tube, second switch tube (Q 2 ). A first end of the first switch tube is used for being connected to a positive end of a first power supply and a second end of the first switch tube is connected to a positive input end of a first driving module. A first end of the second switch tube is used for being connected to a positive end of a second power supply and a second end of the second switch tube is connected to a positive input end of a second driving module.

Claims (21)

1. A direct-current power supply parallel input anti-reverse-connection circuit, comprising: a first power supply, a second power supply, a first switching tube, a second switching tube, a first driving module, and a second driving module; wherein

a first end of the first switching tube is configured to be connected with a positive end of the first power supply, and a second end of the first switching tube is connected with a positive input end of the first driving module;

a negative input end of the first driving module is configured to be connected with a negative end of the first power supply, wherein the negative input end of the first driving module is a grounding end;

the first driving module converts a power supply and provides the converted power supply to a load;

a first end of the second switching tube is configured to be connected with a positive end of the second power supply, and a second end of the second switching tube is connected with a positive input end of the second driving module;

a negative input end of the second driving module is configured to be connected with a negative end of the second power supply, wherein the negative input end of the second driving module is a grounding end;

the second driving module converts a power supply and then provides the converted power supply to the load;

wherein, when the second power supply is reversely connected, the first switching tube is turned on, and the second switching tube is turned off, so as to prevent a current from flowing to the negative end of the second power supply from the positive end of the first power supply; and when the first power supply is reversely connected, the first switching tube is turned off, and the second switching tube is turned on so as to prevent a current from flowing to the negative end of the first power supply from the positive end of the second power supply;

wherein, the first switching tube is a first N-channel Metal Oxide Semiconductor (NMOS) tube; and

a source electrode of the first NMOS tube is configured to be connected with the positive end of the first power supply, a drain electrode of the first NMOS tube is connected with the positive input end of the first driving module, and a gate electrode of the first NMOS tube is connected with a first driving circuit, wherein the first driving circuit provides a high level for the gate electrode of the first NMOS tube.

2. The circuit according to claim 1 , wherein, the first switching tube and the second switching tube are both Metal Oxide Semiconductor (MOS) tubes.

3. The circuit according to claim 1 , wherein, the second switching tube is a second NMOS tube;

a source electrode of the second NMOS tube is configured to be connected with the positive end of the second power supply, a drain electrode of the second NMOS tube is connected with the positive input end of the second driving module, and a gate electrode of the second NMOS tube is connected with a second driving circuit, wherein the second driving circuit provides a high level for the gate electrode of the second NMOS tube.

4. The circuit according to claim 1 , further comprising: a first safety fuse, and a third NMOS tube, wherein

the first switching tube is configured to be connected with the positive end of the first power supply through the first safety fuse; and

a drain electrode of the third NMOS tube is connected with the negative end of the first power supply, a source electrode of the third NMOS tube is connected with the negative input end of the first driving module, and a gate electrode of the third NMOS tube is connected with a third driving circuit, wherein the third driving circuit provides a high level for the gate electrode of the third NMOS tube.

5. The circuit according to claim 1 , further comprising: a second safety fuse, and a fourth MOS tube, wherein

the second switching tube is configured to be connected with the positive end of the second power supply through the second safety fuse; and

a drain electrode of the fourth NMOS tube is connected with the negative end of the second power supply, a source electrode of the fourth NMOS tube is connected with the negative input end of the second driving module, and a gate electrode of the fourth NMOS tube is connected with a fourth driving circuit, wherein the fourth driving circuit provides a high level for the gate electrode of the fourth NMOS tube.

6. The circuit according to claim 1 , wherein, the first power supply and the second power supply are −48 V power supplies.

7. A server, comprising the direct-current power supply parallel input anti-reverse-connection circuit of claim 1 , and comprising: a direct-current power supply parallel input anti-reverse-connection circuit module and a load.

Assignments (2)
LICENSE Recorded Jun 30, 2026
From: IEIT SYSTEMS CO., LTD
To: AIVRES SYSTEMS INC.
Reel/Frame 075857/0939 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2022
From: GAO, PENGFEI
To: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
Reel/Frame 059379/0247 →
Priority Claims (1)
CN 201910927263.X · Sep 27, 2019 · national
Continuity (1)
Related Publication 20220344931A1 · Oct 27, 2022