IP Library › Granted Patent US 12,230,693
Granted Patent B2
US 12,230,693 · App. 17/765,295 · Granted Feb 18, 2025

Semiconductor device and manufacturing method therefor

Inventors: Nailong He (Wuxi, CN); Sen Zhang (Wuxi, CN)
Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
H01L29/66681H01L21/0415H01L21/76202H01L29/66492H01L29/7816H01L29/0847
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Quick Facts
Patent No.
US 12,230,693
App. No.
17/765,295
Granted
Feb 18, 2025
Kind
B2
Abstract

A semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a semiconductor substrate. A first drift region is formed in the semiconductor substrate. A gate structure is formed on the semiconductor substrate A part of the gate structure covers a part of the first drift region. A first trench is formed in the first drift region, and a drain region is formed in the semiconductor substrate at the bottom of the first trench.

Claims (32)

1. A semiconductor device, comprising:

a semiconductor substrate;

a first drift region formed in the semiconductor substrate, a first trench being formed in the first drift region;

a gate structure formed on the semiconductor substrate, a part of the gate structure covering a part of the first drift region;

a drain region formed at a bottom of the first trench, wherein edges of the drain region are in contact with sidewalls of the first trench;

a source region, the source region and the drain region being respectively disposed on two sides of the gate structure; and

a second drift region located in the semiconductor substrate, the second drift region and the first drift region being respectively disposed on two sides of the gate structure, a part of the gate structure covering a part of the second drift region.

2. The semiconductor device according to claim 1 , wherein the source region is disposed on a surface of the semiconductor substrate.

3. The semiconductor device according to claim 1 , wherein a second trench is formed in the second drift region, and the source region is formed in the semiconductor substrate at a bottom of the second trench.

4. The semiconductor device according to claim 1 , further comprising:

an isolation structure disposed on outer sides of the drain region and the source region.

5. The semiconductor device according to claim 4 , wherein the isolation structure comprises a trench isolation structure or a local oxidation of silicon isolation.

6. The semiconductor device according to claim 1 , wherein the drain region is formed in the first drift region.

7. The semiconductor device according to claim 3 , wherein the source region is formed in the second drift region.

8. A manufacturing method for a semiconductor device, comprising steps of:

providing a semiconductor substrate, and forming a first drift region in the semiconductor substrate;

forming a gate structure on the semiconductor substrate, with a part of the gate structure covering a part of the first drift region;

etching the first drift region to form a first trench in the first drift region;

performing ion implantation to form a drain region at a bottom of the first trench, wherein edges of the drain region are in contact with sidewalls of the first trench

forming a second drift region in the semiconductor substrate, the second drift region and the first drift region being respectively disposed on two sides of the gate structure, and a part of the gate structure covering a part of the second drift region;

etching the second drift region to form a second trench in the second drift region; and

performing ion implantation to form a source region in the semiconductor substrate at a bottom of the second trench.

9. The manufacturing method according to claim 8 , further comprising:

performing ion implantation to form a source region on a surface of the semiconductor substrate.

10. The manufacturing method according to claim 8 , wherein the forming the first drift region in the semiconductor substrate and the forming the second drift region in the semiconductor substrate are performed in one same step, the forming the first trench in the first drift region and the forming the second trench in the second drift region are performed in one same step.

11. The manufacturing method according to claim 8 , wherein the step of forming the drain region in the semiconductor substrate at the bottom of the first trench comprises forming the drain region in the first drift region.

12. The manufacturing method according to claim 9 , wherein the step of forming the source region in the semiconductor substrate at the bottom of the second trench comprises forming the source region in the second drift region.

13. The semiconductor device according to claim 1 , wherein the semiconductor device comprises an LDMOS device or an EDMOS device.

14. The semiconductor device according to claim 1 , wherein the gate structure comprises a gate dielectric layer and a gate material layer sequentially stacked from bottom to top.

15. The semiconductor device according to claim 14 , wherein the gate material layer comprises one or more of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer, and a metal silicide layer.

16. The semiconductor device according to claim 1 , further comprising spacer structures located at two sides of the gate structure and close to the gate structure and formed on the semiconductor substrate.

17. The manufacturing method according to claim 9 , wherein, the source region is formed at the same time of forming the drain region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2022
From: HE, NAILONG; ZHANG, SEN
To: CSMC TECHNOLOGIES FAB2 CO., LTD.
Reel/Frame 059445/0911 →
Priority Claims (1)
CN 201911395825.7 · Dec 30, 2019 · national
Continuity (1)
Related Publication 20220367682A1 · Nov 17, 2022
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Cited By (2)
US 12,648,172 US 12,684,805