Shift register unit, signal generation unit circuit, driving method and display device

1. A shift register unit, comprising a first node control circuit, a second node control circuit and an output circuit, wherein,

the first node control circuit is configured to control a potential of a first node;

the second node control circuit is electrically connected to a second node, a third node, a first voltage terminal, an initial voltage terminal and a first clock signal terminal, and is configured to control a potential of the third node under the control a first voltage signal and an initial voltage signal, and control to connect the third node and the second node under the control of a first clock signal; the first voltage terminal is used for providing the first voltage signal, the initial voltage terminal is used for providing the initial voltage signal, and the first clock signal terminal is used for providing the first clock signal;

the output circuit is electrically connected to an output terminal, the first node, the second node, a second clock signal terminal and a second voltage terminal, is configured to maintain the potential of the first node and a potential of the second node, and control to connect the output terminal and the second clock signal terminal under the control of the potential of the first node, and control to connect the output terminal and the second voltage terminal under the control of the potential of the second node.

2. The shift register unit according to claim 1 , wherein the first node control circuit is connected to the first clock signal terminal, the first node, and the initial voltage terminal, and configured to control the potential of the first node according to the first clock signal provided by the first clock signal terminal and the initial voltage signal provided by the initial voltage terminal.

3. The shift register unit according to claim 2 , wherein the first node control circuit comprises a first transistor;

a control electrode of the first transistor is electrically connected to the first clock signal terminal, a first electrode of the first transistor is electrically connected to the initial voltage terminal, and a second electrode of the first transistor is electrically connected to the first node;

the second node control circuit may include a second transistor, a third transistor, and a fourth transistor, wherein, a control electrode of the second transistor and a first electrode of the second transistor are both electrically connected to the first voltage terminal, and a second electrode of the second transistor is electrically connected to the third node;

a control electrode of the third transistor is electrically connected to the initial voltage terminal, a first electrode of the third transistor is electrically connected to the third node, and a second electrode of the third transistor is electrically connected to the second voltage terminal;

a control electrode of the fourth transistor is electrically connected to the first clock signal terminal, a first electrode of the fourth transistor is electrically connected to the third node, and a second electrode of the fourth transistor is electrically connected to the second node.

4. The shift register unit according to claim 1 , wherein the first node control circuit includes a first control sub-circuit, a second control sub-circuit and a first node control sub-circuit;

the first control sub-circuit is electrically connected to the first voltage terminal, the first clock signal terminal, the second node and a fourth node, and is configured to control to connect the fourth node and the first voltage terminal under the control of the first clock signal, and control to connect the fourth node and the first clock signal terminal under the control of the potential of the second node, and configured to maintain a potential of the fourth node;

the second control sub-circuit is electrically connected to the fourth node, the second clock signal terminal and a fifth node, and is configured to control to connect the fifth node and the second clock signal terminal under the control of the potential of the fourth node;

the first node control sub-circuit is electrically connected to the second clock signal terminal, the fifth node, the first node, the second node and the second voltage terminal, is configured to control to connect the first node and the fifth node under the control of the second clock signal provided by the second clock signal terminal, control to connect the first node and the second voltage terminal under the control of the potential of the second node.

5. The shift register unit according to claim 4 , wherein the first control sub-circuit includes a first transistor, a fifth transistor and a control capacitor, the second control sub-circuit includes a sixth transistor, and the first node control sub-circuit includes a seventh transistor and an eighth transistor,

a control electrode of the first transistor is electrically connected to the first clock signal terminal, a first electrode of the first transistor is electrically connected to the first voltage terminal, and a second electrode of the first transistor is electrically connected to the fourth node;

a control electrode of the fifth transistor is electrically connected to the second node, a first electrode of the fifth transistor is electrically connected to the fourth node, and a second electrode of the fifth transistor is electrically connected to the first clock signal terminal;

a first terminal of the control capacitor is electrically connected to the fourth node, and a second terminal of the control capacitor is electrically connected to the fifth node;

a control electrode of the sixth transistor is electrically connected to the fourth node, a first electrode of the sixth transistor is electrically connected to the second clock signal terminal, and a second electrode of the sixth transistor is electrically connected to the fifth node;

a control electrode of the seventh transistor is electrically connected to the second clock signal terminal, a first electrode of the seventh transistor is electrically connected to the fifth node, and a second electrode of the seventh transistor is electrically connected to the first node;

a control electrode of the eighth transistor is electrically connected to the second node, a first electrode of the eighth transistor is electrically connected to the first node, and a second electrode of the eighth transistor is electrically connected to the second voltage terminal.

6. The shift register unit according to claim 4 , wherein the second node control circuit is connected to the second clock signal terminal and the fourth node, and is also configured to control to connect the second node and the second voltage terminal under the control of the potential of the fourth node and the second clock signal provided by the second clock signal terminal.

7. The shift register unit according to claim 6 , wherein the second node control circuit includes a second transistor, a third transistor, a fourth transistor, a ninth transistor, and a tenth transistor, wherein,

a control electrode of the second transistor and a first electrode of the second transistor are both electrically connected to the first voltage terminal, and a second electrode of the second transistor is electrically connected to the third node;

a control electrode of the third transistor is electrically connected to the initial voltage terminal, a first electrode of the third transistor is electrically connected to the third node, and a second electrode of the third transistor is electrically connected to the second voltage terminal;

a control electrode of the fourth transistor is electrically connected to the first clock signal terminal, a first electrode of the fourth transistor is electrically connected to the third node, and a second electrode of the fourth transistor is electrically connected to the second node;

a control electrode of the ninth transistor is electrically connected to the fourth node, and a first electrode of the ninth transistor is electrically connected to the second voltage terminal;

a control electrode of the tenth transistor is electrically connected to the second clock signal terminal, a first electrode of the tenth transistor is electrically connected to a second electrode of the ninth transistor, and a second electrode of the tenth transistor is electrically connected to the second node.

8. The shift register unit according to claim 6 , wherein the second node control circuit comprises a second transistor, a third transistor, a fourth transistor, and a ninth transistor;

a control electrode of the second transistor and a first electrode of the second transistor are both electrically connected to the first voltage terminal, and a second electrode of the second transistor is electrically connected to the third node;

a control electrode of the third transistor is electrically connected to the initial voltage terminal, a first electrode of the third transistor is electrically connected to the third node, and a second electrode of the third transistor is electrically connected to the second voltage terminal;

a control electrode of the fourth transistor is electrically connected to the first clock signal terminal, a first electrode of the fourth transistor is electrically connected to the third node, and a second electrode of the fourth transistor is electrically connected to the second node;

a control electrode of the ninth transistor is electrically connected to the fourth node, a first electrode of the ninth transistor is electrically connected to the second voltage terminal, and a second electrode of the ninth transistor is electrically connected to the second node.

9. The shift register unit according to claim 1 , wherein the output circuit comprises a first output transistor, a second output transistor, a first output capacitor and a second output capacitor;

a control electrode of the first output transistor is electrically connected to the first node, a first electrode of the first output transistor is electrically connected to the second clock signal terminal, and a second electrode of the first output transistor is electrically connected to the output terminal;

a first terminal of the first output capacitor is electrically connected to the first node, and a second terminal of the first output capacitor is electrically connected to the output terminal;

a control electrode of the second output transistor is electrically connected to the second node, a first electrode of the second output transistor is electrically connected to the output terminal, and a second electrode of the second output transistor is electrically connected to the second voltage terminal;

a first terminal of the second output capacitor is electrically connected to the second node, and a second terminal of the second output capacitor is electrically connected to the second voltage terminal.

10. A driving method, applied to the shift register unit according to claim 1 , the driving method comprising:

controlling, by the first node control circuit, the potential of the first node;

controlling, by the second node control circuit, the potential of the third node under the control of the first voltage signal and the initial voltage signal, and controlling to connect to disconnect the third node and the second node under the control of the first clock signal;

controlling, by the output circuit, to connect or disconnect the output terminal and the second clock signal terminal under the control of the potential of the first node, and controlling to connect or disconnect the output terminal and the second voltage terminal under the control of the potential of the second node.

11. The driving method according to claim 10 , wherein the step of controlling, by the first node control circuit, the potential of the first node comprises:

controlling, by the first node control circuit, the potential of the first node according to the first clock signal and the initial voltage signal.

12. The driving method according to claim 10 , wherein the first node control circuit includes a first control sub-circuit, a second control sub-circuit and a first node control sub-circuit; the step of controlling, by the first node control circuit, the potential of the first node includes:

controlling, by the first control sub-circuit, to connect or disconnect a fourth node and the first voltage terminal under the control of the first clock signal, and controlling, by the first control sub-circuit, to connect or disconnect the fourth node and the first clock signal terminal under the control of the potential of the second node, and maintaining, by the first control sub-circuit, a potential of the fourth node;

controlling, by the second control sub-circuit, to connect or disconnect a fifth node and a second clock signal terminal under the control of the potential of the fourth node;

controlling, by the first node control sub-circuit, to connect or disconnect the first node and the fifth node under the control of the second clock signal, and controlling, by the first node control sub-circuit, to connect or disconnect the first node and the second voltage terminal under the control of the potential of the second node;

controlling, by the second node control circuit, to connect or disconnect the second node and the second voltage terminal under the control of the potential of the fourth node and the second clock signal.

13. A gate driving circuit comprising a plurality of stages of shift register units according to claim 1 ;

except for a first stage of shift register unit, an initial voltage terminal of each stage of the shift register unit is electrically connected to an output terminal of an adjacent previous stage of the shift register unit.