Method, arrangement and computer program product for debugging a printed circuit board

1. A method for debugging a printed circuit board, and/or at least one test-pattern for such printed circuit board, said printed circuit board comprising a plurality of devices mounted on said printed circuit board having circuit terminals for interconnecting said devices, said devices comprising at least one boundary-scan compliant device having boundary-scan compliant circuit terminals and comprising a boundary-scan register of boundary-scan cells of said boundary-scan compliant circuit terminals, said method using an electronic processing unit and comprising the steps of:

retrieving, by said processing unit, boundary-scan properties of said at least one boundary-scan compliant device, said boundary-scan properties at least comprising a listing of boundary-scan compliant circuit terminals of said at least one boundary-scan compliant device;

retrieving, by said processing unit, connectivity properties of said plurality of devices mounted on said printed circuit board, said connectivity properties at least comprising a listing of interconnects between said circuit terminals of said devices;

displaying, by said processing unit, a circuit graph of at least a part of said devices mounted on said printed circuit board, said circuit graph comprising at least one device of said plurality of devices mounted on said printed circuit board and a least one further device from said plurality of devices which comprises a circuit terminal interconnected to a circuit terminal of said device for visualizing at least said device, said further device and interconnects between said devices for debugging said printed circuit board; wherein said device is determined by receiving, by said processing unit, a selection from one of the group of: said printed circuit board, said devices mounted on said printed circuit board, and a circuit terminal of one of said devices mounted on said printed circuit board.

2. The method of claim 1 , wherein said device is determined by receiving, by said processing unit, a selection of at least one printed circuit board.

3. The method of claim 1 , wherein said device is determined by receiving, by said processing unit, a selection of at least one device mounted on a printed circuit board of said selection of said at least one printed circuit board.

4. The method of claim 1 , wherein said device is determined by receiving, by said processing unit, a selection of a circuit terminal of one of said devices mounted on said printed circuit board.

5. The method of claim 1 , wherein said step of displaying, by said processing unit, comprises displaying a circuit graph of at least part of said devices, and wherein for each of said displayed devices properties are displayed corresponding to said device.

6. The method of claim 5 , wherein said properties comprise one or more of the group consisting of: number of circuit terminals, number of boundary-scan compliant circuit terminals, type of device, consecutive number identification of said type of device and interconnected circuit terminal.

7. The method of claim 1 , wherein said method further comprises: determining boundary-scan transparent devices from said listing of boundary scan properties and said connectivity properties, wherein said transparent devices are defined by devices through which data of a boundary-scan test is passed through said device in a non-adjusted manner.

8. The method of claim 1 , wherein said method further comprises: subjecting, by said processing unit, at least one boundary-scan compliant circuit terminal of a chain boundary-scan compliant circuit terminals of said boundary-scan compliant devices mounted on said printed circuit board to a boundary-scan test.

9. The method of claim 8 , wherein said boundary-scan test is operated for generating said connectivity properties of said devices mounted on said printed circuit board.

10. The method of claim 1 , wherein said boundary scan properties are retrieved from a Boundary Scan Description Language, BSDL, file of said at least one boundary-scan compliant device.

11. The method of claim 1 , further comprising a graphical interface device, wherein at least one of said steps of displaying, receiving, operating and presenting are controlled from said graphical interface device.

12. A non-transitional computer program product comprising a data storage device storing thereon computer program code data arranged for performing the method of claim 1 , when said program code data are loaded into a memory of said electronic processing unit and are executed by said electronic processing unit.

13. A debugging arrangement for debugging a printed circuit board, and/or at least one test-pattern for such printed circuit board, said printed circuit board comprising a plurality of devices mounted on said printed circuit board having circuit terminals for interconnecting said devices, said devices comprising at least one boundary-scan compliant device having boundary-scan compliant circuit terminals and comprising a boundary-scan register of boundary-scan cells of said boundary-scan compliant circuit terminals, said debugging arrangement comprising an electronic processing unit configured for:

retrieving boundary-scan properties of said at least one boundary-scan compliant device, said boundary-scan properties at least comprising a listing of boundary-scan compliant circuit terminals of said at least one boundary-scan compliant device;

retrieving connectivity properties of said plurality of devices mounted on said printed circuit board, said connectivity properties at least comprising a listing of interconnects between said circuit terminals of said devices;

displaying a circuit graph of at least a part of said devices mounted on said printed circuit board, said circuit graph comprising at least one device of said plurality of devices mounted on said printed circuit board and a least one further device from said plurality of devices which comprises a circuit terminal interconnected to a circuit terminal of said device for visualizing at least said device, said further device and interconnects between said devices for debugging said printed circuit board; wherein said device is determined by receiving, by a processing unit, a selection from one of the group of: said printed circuit board, said devices mounted on said printed circuit board, and a circuit terminal of one of said devices mounted on said printed circuit board.

14. A method for debugging a printed circuit board, and/or at least one test-pattern for such printed circuit board, said printed circuit board comprising a plurality of devices mounted on said printed circuit board having circuit terminals for interconnecting said devices, said devices comprising at least one boundary-scan compliant device having boundary-scan compliant circuit terminals and comprising a boundary-scan register of boundary-scan cells of said boundary-scan compliant circuit terminals, said method using an electronic processing unit and comprising the steps of:

retrieving, by said processing unit, boundary-scan properties of said at least one boundary-scan compliant device, said boundary-scan properties at least comprising a listing of boundary-scan compliant circuit terminals of said at least one boundary-scan compliant device;

retrieving, by said processing unit, connectivity properties of said plurality of devices mounted on said printed circuit board, said connectivity properties at least comprising a listing of interconnects between said circuit terminals of said devices;

identifying, by user input, at least one device of said plurality of devices by receiving a selection from one of the group of: said printed circuit board, said devices mounted on said printed circuit board, and a circuit terminal of one of said devices mounted on said printed circuit board; and

displaying, by said processing unit, a circuit layout visualization comprising the at least one device of said plurality of devices with a first circuit terminal and a least one further device from said plurality of devices with a second circuit terminal interconnected to the first circuit terminal, the circuit layout visualization for debugging said printed circuit board.