Array substrate and display device
The present disclosure is related to an array substrate and a display device. The array substrate has a display area and a peripheral area surrounding the display area. The array substrate includes a gate material layer and a source and drain material layer that are sequentially stacked on a base substrate. The array substrate further includes a driving signal line. The driving signal line includes a first sub-signal line and a second sub-signal line. The first sub-signal line is arranged in the gate material layer and extends from the peripheral area to the display area. The second sub-signal line is arranged in the source and drain material layer and located at least in the display area. The first sub-signal line and the second sub-signal line are electrically connected through a via hole.
1. An array substrate having a display area and a peripheral area surrounding the display area, wherein the array substrate further comprises:
a base substrate;
a gate material layer arranged on a side of the base substrate; and
a source and drain material layer arranged on a side of the gate material layer away from the base substrate;
wherein the array substrate further comprises a driving signal line, the driving signal line comprises a first sub-signal line and a second sub-signal line, the first sub-signal line is arranged in the gate material layer and extends from the peripheral area to the display area, the second sub-signal line is arranged in the source and drain material layer and located at least in the display area, and the first sub-signal line and the second sub-signal line are electrically connected through a via hole.
2. The array substrate according to claim 1 , wherein the source and drain material layer comprises:
a first source and drain material sub-layer arranged on the side of the gate material layer away from the base substrate; and
a second source and drain material sub-layer arranged on a side of the first source and drain material sub-layer away from the base substrate;
wherein the second sub-signal line is arranged in the first source and drain material sub-layer or the second source and drain material sub-layer.
3. The array substrate according to claim 2 , wherein:
the driving signal line comprises a gate driving signal line;
the first sub-signal line comprises a first sub-gate driving line;
the second sub-signal line comprises a second sub-gate driving line;
the first sub-gate driving line is arranged in the gate material layer and extends from the peripheral area to the display area;
the second sub-gate driving line is arranged in the first source and drain material sub-layer or in the second source and drain material sub-layer and the second sub-gate driving line is located at least in the display area; and
the first sub-gate driving line and the second sub-gate driving line are electrically connected through a via hole.
4. The array substrate according to claim 2 , wherein:
the driving signal line comprises an enable signal line;
the first sub-signal line comprises a first sub-enable signal line;
the second sub-signal line comprises a second sub-enable signal line;
the first sub-enable signal line is arranged in the gate material layer and extends from the peripheral area to the display area;
the second sub-enable signal line is arranged in the first source and drain material sub-layer or in the second source and drain material sub-layer and the second sub-enable signal line is located at least in the display area; and
the first sub-enable signal line and the second sub-enable signal line are electrically connected through a via hole.
5. The array substrate according to claim 2 , wherein:
the driving signal line comprises a reset signal line;
the first sub-signal line comprises a first sub-reset signal line;
the second sub-signal line comprises a second sub-reset signal line;
the first sub-reset signal line is arranged in the gate material layer and extends from the peripheral area to the display area;
the second sub-reset signal line is arranged in the first source and drain material sub-layer or in the second source and drain material sub-layer and the second sub-reset signal line is located at least in the display area; and
the first sub-reset signal line and the second sub-reset signal line are electrically connected through a via hole.
6. The array substrate according to claim 2 , wherein the first sub-signal line and the second sub-signal line extend in a same direction, or extend in different directions.
7. The array substrate according to claim 6 , wherein the array substrate further comprises a power line, the power line comprises a first sub-power line and a second sub-power line, the first sub-power line is arranged in the first source and drain material sub-layer, the second sub-power line is arranged in the second source and drain material sub-layer, and the first sub-power line and the second sub-power line are electrically connected through a via hole.
8. The array substrate according to claim 7 , wherein the second sub-signal line and the second sub-power line are both located in the second source and drain material sub-layer, and the second sub-signal line and the second sub-power line extend in a same direction and are arranged in another direction.
9. The array substrate according to claim 8 , wherein the first sub-signal line extends in a first direction, the first sub-power line extends in a second direction, the second sub-signal line and the second sub-power line both extend in the first direction and are arranged along the second direction, and the first direction and the second direction intersect.
10. The array substrate according to claim 7 , wherein the second sub-signal line is further located in the peripheral area, and the first sub-signal line and the second sub-signal line are electrically connected through the via hoe in the peripheral area.
11. The array substrate according to claim 1 , wherein a line width of the second sub-signal line is greater than a line width of the first sub-signal line.
12. The array substrate according to claim 2 , further comprising:
an interlayer dielectric layer arranged between a second gate material layer and the first source and drain material sub-layer;
an insulating layer arranged between the first source and drain material sub-layer and the second source and drain material sub-layer; and
a planarization layer arranged between the first source and drain material sub-layer and the second source and drain material sub-layer, and located on a side of the insulating layer away from the first source and drain material sub-layer.
13. The array substrate according to claim 1 , wherein the array substrate comprises a GOA driving circuit, and the first sub-signal line is connected to an output terminal of the GOA driving circuit.
14. The array substrate according to claim 1 , wherein the gate material layer comprises a first gate material layer and a second gate material layer that are stacked and a gate insulating layer between the first gate material layer and the second gate material layer, and the first sub-signal line is located in the first gate material layer or the second gate material layer.
15. A display device, comprising an array substrate having a display area and a peripheral area surrounding the display area, wherein the array substrate further comprises:
a base substrate;
a gate material layer arranged on a side of the base substrate; and
a source and drain material layer arranged on a side of the gate material layer away from the base substrate;
wherein the array substrate further comprises a driving signal line, the driving signal line comprises a first sub-signal line and a second sub-signal line, the first sub-signal line is arranged in the gate material layer and extends from the peripheral area to the display area, the second sub-signal line is arranged in the source and drain material layer and located at least in the display area, and the first sub-signal line and the second sub-signal line are electrically connected through a via hole.
16. The display device according to claim 15 , wherein the source and drain material layer comprises:
a first source and drain material sub-layer arranged on the side of the gate material layer away from the base substrate; and
a second source and drain material sub-layer arranged on a side of the first source and drain material sub-layer away from the base substrate;
wherein the second sub-signal line is arranged in the first source and drain material sub-layer or the second source and drain material sub-layer.
17. The display device according to claim 16 , wherein:
the driving signal line comprises a gate driving signal line;
the first sub-signal line comprises a first sub-gate driving line;
the second sub-signal line comprises a second sub-gate driving line;
the first sub-gate driving line is arranged in the gate material layer and extends from the peripheral area to the display area;
the second sub-gate driving line is arranged in the first source and drain material sub-layer or in the second source and drain material sub-layer and the second sub-gate driving line is located at least in the display area; and
the first sub-gate driving line and the second sub-gate driving line are electrically connected through a via hole.
18. The display device according to claim 16 , wherein:
the driving signal line comprises an enable signal line;
the first sub-signal line comprises a first sub-enable signal line;
the second sub-signal line comprises a second sub-enable signal line;
the first sub-enable signal line is arranged in the gate material layer and extends from the peripheral area to the display area;
the second sub-enable signal line is arranged in the first source and drain material sub-layer or in the second source and drain material sub-layer and the second sub-enable signal line is located at least in the display area; and
the first sub-enable signal line and the second sub-enable signal line are electrically connected through a via hole.
19. The display device according to claim 16 , wherein:
the driving signal line comprises a reset signal line;
the first sub-signal line comprises a first sub-reset signal line;
the second sub-signal line comprises a second sub-reset signal line;
the first sub-reset signal line is arranged in the gate material layer and extends from the peripheral area to the display area;
the second sub-reset signal line is arranged in the first source and drain material sub-layer or in the second source and drain material sub-layer and the second sub-reset signal line is located at least in the display area; and
the first sub-reset signal line and the second sub-reset signal line are electrically connected through a via hole.
20. The display device according to claim 16 , wherein the first sub-signal line and the second sub-signal line extend in a same direction, or extend in different directions.