IP Library › Granted Patent US 12,604,610
Granted Patent B2
US 12,604,610 · App. 17/777,793 · Granted Apr 14, 2026

Display panel and manufacturing method therefor, and display device

Inventor: Shantao Chen (Beijing, CN)
Assignee: BOE Technology Group Co., Ltd.
H10K59/1201H10K59/122H10K59/173H10K59/80521
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Quick Facts
Patent No.
US 12,604,610
App. No.
17/777,793
Granted
Apr 14, 2026
Kind
B2
Abstract

Provided are a display panel and a manufacturing method therefor, and a display device. The display panel includes: a substrate, a pixel defining layer located on the substrate, and a cathode isolation structure located on the pixel defining layer. The cathode isolation structure includes at least a first isolation sub-layer and a second isolation sub-layer located between the pixel defining layer and the first isolation sub-layer, the cross section of the second isolation sub-layer is smaller than that of the first isolation sub-layer, and an orthographic projection, on the substrate, of the second isolation sub-layer falls within an orthographic projection range, on the substrate, of the first isolation sub-layer.

Claims (45)

1 . A display panel, comprising:

a substrate;

a pixel definition layer on a side of the substrate;

a cathode isolation structure located on a side of the pixel definition layer away from the substrate, and the cathode isolation structure comprising: a first isolation sub-layer, and a second isolation sub-layer located between the pixel definition layer and the first isolation sub-layer, wherein a cross section of the second isolation sub-layer is smaller than a cross section of the first isolation sub-layer in a direction parallel to the substrate, and an orthographic projection of the second isolation sub-layer on the substrate falls within a range of an orthographic projection of the first isolation sub-layer on the substrate;

wherein the cathode isolation structure further comprises: a third isolation sub-layer located between the pixel definition layer and the second isolation sub-layer;

the cross section of the second isolation sub-layer is smaller than a cross section of the third isolation sub-layer in the direction parallel to the substrate, and the orthographic projection of the second isolation sub-layer on the substrate falls within a range of an orthographic projection of the third isolation sub-layer on the substrate;

wherein a material of the first isolation sub-layer and a material of the third isolation sub-layer are inorganic materials, and a material of the second isolation sub-layer is an organic material;

wherein the material of the first isolation sub-layer comprises silicon oxide, and the material of the third isolation sub-layer comprises silicon nitride.

2 . The display panel according to claim 1 , wherein a center of the cross section of the first isolation sub-layer, a center of the cross section of the second isolation sub-layer and a center of the cross section of the third isolation sub-layer that are stacked coincide in the direction parallel to the substrate.

3 . The display panel according to claim 1 , wherein the orthographic projection of the third isolation sub-layer on the substrate coincides with the orthographic projection of the first isolation sub-layer on the substrate.

4 . The display panel according to claim 1 , wherein a thickness of the first isolation sub-layer is not less than 200 nanometers.

5 . The display panel according to claim 1 , wherein materials of the first isolation sub-layer, the second isolation sub-layer and the third isolation sub-layer are different from each other.

6 . The display panel according to claim 1 , wherein the material of the second isolation sub-layer comprises polyimide.

7 . The display panel according to claim 1 , wherein the display panel further comprises: a cathode located on a side of the pixel definition layer and the cathode isolation structure away from the substrate;

the cathode comprises: a first portion located on a side of the first isolation sub-layer facing away from the substrate, and a second portion located in a region outside the cathode isolation structure, wherein the first portion and the second portion are disconnected from each other.

8 . The display panel according to claim 7 , wherein the pixel definition layer comprises a plurality of pixel openings;

the display panel further comprises: an anode located in the pixel openings;

a light-emitting function layer located in the pixel openings and between the anode and the second portion of the cathode.

9 . A manufacturing method for the display panel according to claim 1 , comprising:

forming the pixel definition layer on the substrate;

forming the second isolation sub-layer on the pixel definition layer and forming the first isolation sub-layer on the second isolation sub-layer; wherein the cross section of the second isolation sub-layer is smaller than the cross section of the first isolation sub-layer in the direction parallel to the substrate, and the orthographic projection of the second isolation sub-layer on the substrate falls within the range of an orthographic projection of the first isolation sub-layer on the substrate.

10 . The method according to claim 9 , wherein before forming the second isolation sub-layer on the pixel definition layer, the method further comprises:

forming a third isolation sub-layer on the pixel definition layer; wherein the cross section of the second isolation sub-layer is smaller than a cross section of the third isolation sub-layer in the direction parallel to the substrate, and the orthographic projection of the second isolation sub-layer on the substrate falls within a range of an orthographic projection of the third isolation sub-layer on the substrate.

11 . The method according to claim 10 , wherein forming the third isolation sub-layer, the second isolation sub-layer and the first isolation sub-layer on the pixel definition layer, comprises:

forming a whole-layer third isolation sub-layer on the pixel definition layer;

forming a whole-layer second isolation sub-layer on the third isolation sub-layer;

forming a whole-layer first isolation sub-layer on the second isolation sub-layer;

coating photoresist on the whole-layer first isolation sub-layer;

forming a pattern of the photoresist by exposure and development processes;

processing the first isolation sub-layer, the second isolation sub-layer and the third isolation sub-layer sequentially by an etching process so that the orthographic projection of the third isolation sub-layer on the substrate coincides with the orthographic projection of the first isolation sub-layer on the substrate, and over-etching a side surface of the second isolation sub-layer to form a pattern of the first isolation sub-layer, a pattern of the second isolation sub-layer and a pattern of the third isolation sub-layer;

removing the photoresist.

12 . The method according to claim 9 , wherein after forming the first isolation sub-layer on the pixel definition layer, the method further comprises:

forming a pattern of a cathode by a sputtering process, wherein the cathode comprises: a first portion located on a side of the first isolation sub-layer facing away from the substrate, and a second portion located in a region outside the cathode isolation structure, wherein the first portion and the second portion are disconnected from each other.

13 . The method according to claim 12 , wherein before forming the pixel definition layer on the substrate, the method further comprises:

forming a pattern of an anode on the substrate, wherein the pattern of the anode is located within pixel openings of the pixel definition layer to be formed;

before forming the pattern of the cathode, the method further comprises:

forming a light-emitting function layer located on the anode in the pixel openings.

14 . A display device, comprising a display panel, the display panel, comprising:

a substrate;

a pixel definition layer on a side of the substrate;

a cathode isolation structure located on a side of the pixel definition layer away from the substrate, and the cathode isolation structure comprising: a first isolation sub-layer, and a second isolation sub-layer located between the pixel definition layer and the first isolation sub-layer, wherein a cross section of the second isolation sub-layer is smaller than a cross section of the first isolation sub-layer in a direction parallel to the substrate, and an orthographic projection of the second isolation sub-layer on the substrate falls within a range of an orthographic projection of the first isolation sub-layer on the substrate;

wherein the cathode isolation structure further comprises: a third isolation sub-layer located between the pixel definition layer and the second isolation sub-layer;

the cross section of the second isolation sub-layer is smaller than a cross section of the third isolation sub-layer in the direction parallel to the substrate, and the orthographic projection of the second isolation sub-layer on the substrate falls within a range of an orthographic projection of the third isolation sub-layer on the substrate;

wherein a material of the first isolation sub-layer and a material of the third isolation sub-layer are inorganic materials, and a material of the second isolation sub-layer is an organic material;

wherein the material of the first isolation sub-layer comprises silicon oxide, and the material of the third isolation sub-layer comprises silicon nitride.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 18, 2022
From: CHEN, SHANTAO
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 059946/0716 →
Priority Claims (1)
CN 202010124599.5 · Feb 27, 2020 · national
Continuity (1)
Related Publication 20220416197A1 · Dec 29, 2022
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