Granted Patent B2

US 12,362,732 · App. 17/779,675 · Granted Jul 15, 2025

Inventors: Hiroki Inoue (Kanagawa, JP); Seiichi Yoneda (Kanagawa, JP); Yusuke Negoro (Osaka, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

H03K3/011H03K17/56H10F39/80377H04N25/77H10D30/6734H10D30/6755

Abstract

Claims (93)

1. A semiconductor device comprising a first capacitor, a second capacitor, a first circuit and a second circuit,

wherein the first circuit comprises first to n-th (n is an integer of 4 or more) transistors,

wherein the second circuit comprises (n+1)-th to 2n-th transistors,

wherein the semiconductor device further comprises a (2n+1)-th transistor, a (2n+2)-th transistor, a (2n+3)-th transistor, a (2n+4)-th transistor, a first output terminal and a second output terminal,

wherein either sources or drains of the first to n-th transistors are electrically connected to each other,

wherein one of a source and a drain of the (2n+1)-th transistor is electrically connected to ones of the sources or drains of the first to n-th transistors,

wherein one terminal of the first capacitor is electrically connected to the ones of the sources or drains of the first to n-th transistors,

wherein the one of the source and the drain of the (2n+1)-th transistor is electrically connected to the first output terminal,

wherein others of the sources or drains of the first to n-th transistors are electrically connected to each other,

wherein one of a source and a drain of the (2n+3)-th transistor is electrically connected to the others of the source or drains of the first to n-th transistors,

wherein another terminal of the first capacitor is electrically connected to the other of the source and the drain of the (2n+3)-th transistor,

wherein the other of the source and the drain of the (2n+3)-th transistor is electrically connected to a first wiring supplying to a first fixed potential,

wherein a source and a drain of each of the (n+1)-th to 2n-th transistors are connected in series to each other,

wherein one terminal of the second capacitor is electrically connected to the (n+1)-th transistor,

wherein one of a source and a drain of the (2n+2)-th transistor is electrically connected to the (n+1)-th transistor,

wherein the one of the source and the drain of the (2n+2)-th transistor is electrically connected to the second output terminal,

wherein one of a source and a drain of the (2n+4)-th transistor is electrically connected to the 2n-th transistor,

wherein another terminal of the second capacitor is electrically connected to the other of the source and the drain of the (2n+4)-th transistor,

wherein the other of the source and the drain of the (2n+4)-th transistor is electrically connected to a second wiring supplying a second fixed potential,

wherein a gate of the (2n+3)-th transistor is electrically connected to a gate of the (2n+4)-th transistor,

wherein the first fixed potential is higher than the second fixed potential,

wherein first to n-th signals are supplied to the first circuit and the second circuit,

wherein the n-th signal is supplied to a gate of the n-th transistor and a gate of the 2n-th transistor,

wherein the first circuit is configured to output a first potential when each of potentials of the first to n-th signals is lower than or equal to a first reference potential,

wherein the first circuit is configured to output a second potential when at least one of the potentials of the first to n-th signals is higher than the first reference potential,

wherein the second circuit is configured to output a third potential when each of the potentials of the first to n-th signals is higher than a second reference potential, and

wherein the second circuit is configured to output the first potential when at least one of the potentials of the first to n-th signals is lower than or equal to the second reference potential.

2. The semiconductor device according to claim 1 ,

wherein the second potential is a potential corresponding to the first reference potential, and

wherein the third potential is a potential corresponding to the second reference potential.

3. The semiconductor device according to claim 1 ,

wherein the first to 2n-th transistors are n-channel transistors.

4. The semiconductor device according to claim 3 ,

wherein the second reference potential is lower than the first reference potential.

5. The semiconductor device according to claim 3 ,

wherein the second potential and the third potential are lower than the first potential.

6. The semiconductor device according to claim 3 ,

wherein the first to 2n-th transistors include a metal oxide in a channel formation region.

7. The semiconductor device according to claim 1 ,

wherein a gate of the (2n+1)-th transistor is electrically connected to a gate of the (2n+2)-th transistor,

wherein one of a source and a drain of the (2n+2)-th transistor is electrically connected to the second circuit,

wherein the second potential is supplied to the other of the source and the drain of the (2n+1)-th transistor, and

wherein the third potential is supplied to the other of the source and the drain of the (2n+2)-th transistor.

8. A driving method of a semiconductor device comprising:

a first circuit comprising first to n-th (n is an integer of 4 or more) transistors;

a second circuit comprising (n+1)-th to 2n-th transistors;

a (2n+1)-th transistor;

a (2n+2)-th transistor;

a (2n+3)-th transistor;

a (2n+4)-th transistor;

a first capacitor;

a second capacitor;

a first output terminal; and

a second output terminal,

wherein either sources or drains of the first to n-th transistors are electrically connected to each other,

wherein one terminal of the first capacitor is electrically connected to ones of the sources or drains of the first to n-th transistors,

wherein one of a source and a drain of the (2n+1)-th transistor is electrically connected to the ones of the sources or drains of the first to n-th transistors,

wherein the one of the source and the drain of the (2n+1)-th transistor is electrically connected to the first output terminal,

wherein others of the sources or drains of the first to n-th transistors are electrically connected to each other,

wherein another terminal of the first capacitor is electrically connected to others of the sources or drains of the first to n-th transistors,

wherein a source and a drain of each of the (n+1)-th to 2n-th transistors are connected in series to each other,

wherein one terminal of the second capacitor is electrically connected to the (n+1)-th transistor,

wherein one of a source and a drain of the (2n+2)-th transistor is electrically connected to the (n+1)-th transistor,

wherein the one of the source and the drain of the (2n+2)-th transistor is electrically connected to the second output terminal,

wherein another terminal of the second capacitor is electrically connected to the 2n-th transistor,

wherein one of a source and a drain of the (2n+1)-th transistor is electrically connected to the first circuit,

wherein one of a source and a drain of the (2n+2)-th transistor is electrically connected to the second circuit,

wherein one of a source and a drain of the (2n+3)-th transistor is electrically connected to the first circuit, and

wherein one of a source and a drain of the (2n+4)-th transistor is electrically connected to the second circuit,

the method comprising the steps of:

supplying first to n-th signals to the first circuit and the second circuit,

supplying an i-th (i is 1 to n) signal to gates of an i-th transistor and the (n+i)-th transistor,

supplying a first potential to the other of the source and the drain of the (2n+1)-th transistor and the other of the source and the drain of the (2n+2)-th transistor,

supplying a second potential to the other of the source and the drain of the (2n+3)-th transistor,

supplying a third potential to the other of the source and the drain of the (2n+4)-th transistor,

in a first period, turning on the (2n+1)-th transistor and the (2n+2)-th transistor and turning off the (2n+3)-th transistor and the (2n+4)-th transistor, and

in a second period, turning off the (2n+1)-th transistor and the (2n+2)-th transistor and turning on the (2n+3)-th transistor and the (2n+4)-th transistor,

wherein the second potential is higher than the third potential, and

wherein the n-th signal is supplied to a gate of the n-th transistor and a gate of the 2n-th transistor.

9. The driving method of the semiconductor device according to claim 8 ,

wherein the first to 2n-th transistors are n-channel transistors.

10. The driving method of the semiconductor device according to claim 9 ,

wherein the third potential is lower than the second potential.

11. The driving method of the semiconductor device according to claim 9 ,

wherein the second potential and the third potential are lower than the first potential.

12. The semiconductor device according to claim 1 ,

wherein the first reference potential is larger than a difference of potentials of the one terminal and the other terminal of the first capacitor, and

wherein the second reference potential is larger than a difference of potentials of the one terminal and the other terminal of the second capacitor.

13. The semiconductor device according to claim 1 ,

wherein each of the other of the source and the drain of the (2n+1)-th transistor and the other of the source and the drain of the (2n+2)-th transistor is electrically connected to a third wiring supplying to a third fixed potential, and

wherein the third fixed potential is higher than the first fixed potential.

14. The driving method of the semiconductor device according to claim 8 ,

wherein the first potential is higher than the second potential.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (31)