IP Library › Granted Patent US 12,170,059
Granted Patent B2
US 12,170,059 · App. 17/781,720 · Granted Dec 17, 2024

Display substrate, preparation method thereof, and display apparatus with optimized fan-out

Inventors: Shilong Wang (Beijing, CN); Haigang Qing (Beijing, CN); Ziyang Yu (Beijing, CN); Yunsheng Xiao (Beijing, CN); Gukhwan Song (Beijing, CN); Zhiliang Jiang (Beijing, CN); Ming Hu (Beijing, CN)
Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd.; BOE Technology Group Co., Ltd.
G09G3/3233H10K59/1213H10K59/1315G09G2310/08G09G2320/0233
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Quick Facts
Patent No.
US 12,170,059
App. No.
17/781,720
Granted
Dec 17, 2024
Kind
B2
Abstract

A display substrate and a manufacturing method therefor, and a display device are provided in the present disclosure. The display substrate includes a drive circuit layer disposed on a substrate, the drive circuit layer includes a plurality of circuit units, at least one circuit unit of the plurality of circuit units includes a pixel drive circuit, a first power supply line providing a power supply signal to the pixel drive circuit, a data signal line providing a data signal to the pixel drive circuit, and a data fan-out line connected with the data signal line; at least a portion of the first power supply line, the data signal line, and the data fan-out line extends along a second direction and is arranged at intervals along a first direction.

Claims (22)

1. A display substrate, comprising a drive circuit layer disposed on a substrate, wherein the drive circuit layer comprises a plurality of circuit units, at least one circuit unit of the plurality of circuit units comprises a pixel drive circuit, a first power supply line providing a power supply signal to the pixel drive circuit, a data signal line providing a data signal to the pixel drive circuit, and a data fan-out line connected with the data signal line; at least a portion of the first power supply line, the data signal line, and the data fan-out line is arranged at intervals along a first direction, and is extended along a second direction, at least a portion of the data fan-out line is disposed between the first power supply line and the data signal line, the first direction is intersected with the second direction;

wherein an orthographic projection of a portion of the data fan-out line extending along the second direction on a plane of the display substrate is not overlapped with an orthographic projection of the first power supply line on the plane of the display substrate, the orthographic projection of the portion of the data fan-out line extending along the second direction on the plane of the display substrate is not overlapped with an orthographic projection of a body portion of the data signal line on the plane of the display substrate.

2. The display substrate according to claim 1 , wherein the data fan-out line is connected with the data signal line through a via hole.

3. The display substrate according to claim 1 , wherein the data fan-out line at least comprises a first data fan-out line extending along the second direction, and at least a portion of the first data fan-out line is disposed between the first power supply line and the data signal line.

4. The display substrate according to claim 1 , wherein the at least one circuit unit further comprises an initial signal line providing an initial signal to the pixel drive circuit, the initial signal line comprises a first initial signal line of which a body portion extends along the first direction and an initial signal connection line of which a body portion extends along the second direction, the initial signal connection line is connected with the first initial signal line; an orthographic projection of at least one data fan-out line on a plane of the display substrate is at least partially overlapped with an orthographic projection of the initial signal connection line on the plane of the display substrate.

5. The display substrate according to claim 4 , wherein the initial signal connection line is connected with the first initial signal line through a via hole.

6. The display substrate according to claim 4 , wherein the data fan-out line at least comprises a second data fan-out line extending along the second direction, and an orthographic projection of the second data fan-out line on the plane of the display substrate is at least partially overlapped with the orthographic projection of the initial signal connection line on the plane of the display substrate.

7. The display substrate according to claim 6 , wherein the data fan-out line at least comprises a third data fan-out line extending along the first direction, and the third data fan-out line is connected with the first data fan-out line or the second data fan-out line.

8. The display substrate according to claim 1 , wherein the display substrate comprises a display region and a bonding region located at a side of the display region, the first power supply line, the data signal line and the data fan-out line are disposed in the display region, and the bonding region comprises at least one lead line; a first end of the data fan-out line is connected with the data signal line, and a second end of the data fan-out line is connected with the lead line.

9. The display substrate according to claim 1 , wherein in a direction perpendicular to the display substrate, the drive circuit layer comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially disposed on the substrate, and insulating layers are disposed between the first conductive layer and the second conductive layer, between the second conductive layer and the third conductive layer, and between the third conductive layer and the fourth conductive layer; the data signal line and the data fan-out line are disposed in different conductive layers.

10. The display substrate according to claim 9 , wherein the first power supply line and the data signal line are disposed in the third conductive layer, and the data fan-out line is disposed in the fourth conductive layer.

11. The display substrate according to claim 9 , wherein the drive circuit layer further comprises a first initial signal line of which a body portion is extended along the first direction and an initial signal connection line of which a body portion is extended along the second direction, the first initial signal line and the initial signal connection line are disposed in different conductive layers, and the initial signal connection line is connected with the first initial signal line through a via hole.

12. The display substrate according to claim 11 , wherein the first initial signal line is disposed in the second conductive layer and the initial signal connection line is disposed in the third conductive layer.

13. The display substrate according to claim 11 , wherein the initial signal connection line is connected with a first region of an active layer of a first transistor in the pixel drive circuit through a via hole.

14. The display substrate according to claim 11 , wherein the initial signal connection line comprises a first line segment and a second line segment connected with each other, the first line segment is a straight line segment extending along the second direction, the second line segment is a zigzag line segment, and an orthographic projection of the first line segment on a plane of the display substrate is at least partially overlapped with an orthographic projection of the second data fan-out line on the plane of the display substrate.

15. A display device, comprising the display substrate according to claim 1 .

16. A method for manufacturing a display substrate, comprising:

forming a drive circuit layer on a substrate, wherein the drive circuit layer comprises a plurality of circuit units, at least one circuit unit of the plurality of circuit units comprises a pixel drive circuit, a first power supply line providing a power supply signal to the pixel drive circuit, a data signal line providing a data signal to the pixel drive circuit, and a data fan-out line connected with the data signal line; wherein at least a portion of the first power supply line, the data signal line, and the data fan-out line is arranged at intervals along a first direction and is extended along a second direction, at least a portion of the data fan-out line is disposed between the first power supply line and the data signal line, and wherein the first direction is intersected with the second direction;

wherein an orthographic projection of a portion of the data fan-out line extending along the second direction on a plane of the display substrate is not overlapped with an orthographic projection of the first power supply line on the plane of the display substrate, the orthographic projection of the portion of the data fan-out line extending along the second direction on the plane of the display substrate is not overlapped with an orthographic projection of a body portion of the data signal line on the plane of the display substrate.

17. The display substrate according to claim 2 , wherein the display substrate comprises a display region and a bonding region located at a side of the display region, the first power supply line, the data signal line and the data fan-out line are disposed in the display region, and the bonding region comprises at least one lead line; a first end of the data fan-out line is connected with the data signal line, and a second end of the data fan-out line is connected with the lead line.

18. The display substrate according to claim 3 , wherein the display substrate comprises a display region and a bonding region located at a side of the display region, the first power supply line, the data signal line and the data fan-out line are disposed in the display region, and the bonding region comprises at least one lead line; a first end of the data fan-out line is connected with the data signal line, and a second end of the data fan-out line is connected with the lead line.

19. The display substrate according to claim 2 , wherein in a direction perpendicular to the display substrate, the drive circuit layer comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially disposed on the substrate, and insulating layers are disposed between the first conductive layer and the second conductive layer, between the second conductive layer and the third conductive layer, and between the third conductive layer and the fourth conductive layer; the data signal line and the data fan-out line are disposed in different conductive layers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2022
From: WANG, SHILONG; QING, HAIGANG; YU, ZIYANG; XIAO, YUNSHENG; SONG, GUKHWAN; JIANG, ZHILIANG; HU, MING
To: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.; BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 060128/0531 →
Continuity (1)
Related Publication 20240212597A1 · Jun 27, 2024