IP Library Granted Patent US 12,119,421
Granted Patent B2
US 12,119,421 · App. 17/784,276 · Granted Oct 15, 2024

Photodetector

Inventors: Katsuhisa Tanaka (Kanagawa, JP); Yusuke Otake (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H01L31/107H01L31/022408
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Quick Facts
Patent No.
US 12,119,421
App. No.
17/784,276
Granted
Oct 15, 2024
Kind
B2
Abstract

A photodetector including: an amplification region that includes a PN junction provided in a depth direction in a semiconductor layer and that is to be electrically coupled to a cathode; a separation region that defines a pixel region including the amplification region; a hole accumulation region that is provided along a side surface of the separation region and that is to be electrically coupled to an anode; and a gate electrode provided in a region between the amplification region and the hole accumulation region and stacked over the semiconductor layer with a gate insulating film interposed therebetween.

Claims (20)

1. A photodetector, comprising:

an amplification region that includes a PN junction provided in a depth direction in a semiconductor layer and that is to be electrically coupled to a cathode;

a separation region that defines a pixel region including the amplification region;

a hole accumulation region that is provided along a side surface of the separation region and that is to be electrically coupled to an anode; and

a gate electrode provided in a region between the amplification region and the hole accumulation region and stacked over the semiconductor layer with a gate insulating film interposed therebetween.

2. The photodetector according to claim 1 , wherein the amplification region and the pixel region each have a rectangular shape.

3. The photodetector according to claim 1 , wherein the gate electrode is provided in a region surrounding the amplification region.

4. The photodetector according to claim 3 , wherein the gate electrode is provided continuously in the region between the amplification region and the hole accumulation region.

5. The photodetector according to claim 2 , wherein a plurality of the gate electrodes is provided in a respective plurality of regions spaced from each other.

6. The photodetector according to claim 5 , wherein the gate electrodes are provided in the respective regions that are each between corresponding one of side parts of the rectangular shape of the amplification region and the hole accumulation region.

7. The photodetector according to claim 5 , wherein the gate electrodes are provided in the respective regions that are each between corresponding one of vertex parts of the rectangular shape of the amplification region and the hole accumulation region.

8. The photodetector according to claim 5 , wherein the gate electrodes are each provided across the separation region to be continuous with another one of the gate electrodes provided in adjacent one of a plurality of the pixel regions.

9. The photodetector according to claim 8 , wherein the gate insulating film provided in the separation region has a film thickness greater than a film thickness of the gate insulating film provided in the pixel region.

10. The photodetector according to claim 1 , wherein the gate electrode is provided to allow a negative bias voltage to be applied thereto.

11. The photodetector according to claim 10 , wherein the gate electrode is provided to be embedded inside the semiconductor layer.

12. The photodetector according to claim 1 , wherein an electrical conductivity type of the hole accumulation region is a P type.

13. The photodetector according to claim 1 , wherein

a contact that electrically couples to the amplification region and the cathode is provided at an end of the amplification region, and

a P-type region is provided on a front surface of the semiconductor layer in a middle part of the amplification region.

14. The photodetector according to claim 1 , wherein the PN junction is provided by joining an N++-type region onto a P++-type region provided inside the semiconductor layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2022
From: TANAKA, KATSUHISA; OTAKE, YUSUKE
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 060164/0193 →
Priority Claims (1)
JP 2019-233854 · Dec 25, 2019 · national
Continuity (1)
Related Publication 20230040457A1 · Feb 9, 2023