Memory anomaly processing method and system, electronic device, and storage medium
View Patent ↗A memory anomaly processing method and system, an electronic device, and a storage medium. The method includes: reading a memory error quantity of a target memory bank from a memory error register; when the memory error quantity is greater than a preset value, executing a hot-removal operation on the target memory bank; calculating a memory delay parameter, and writing the memory delay parameter into a memory controller, wherein the memory delay parameter is waiting time after the memory controller controls the target memory bank to receive a read/write command; and executing a hot-addition operation on the target memory bank, whereby the memory controller continues to execute a read/write operation on the target memory bank based on the memory delay parameter. It can be seen that, according to the present application, the memory read/write error rate may be reduced.
1. A memory anomaly processing method, comprising:
reading a memory error quantity of a target memory bank from a memory error register;
in response to determining that the memory error quantity is greater than a preset value, executing a hot-removal operation on the target memory bank;
calculating a memory delay parameter, and writing the memory delay parameter into a memory controller, wherein the memory delay parameter is waiting time after the memory controller controls the target memory bank to receive a read/write command; and
executing a hot-addition operation on the target memory bank, whereby the memory controller continues to execute a read/write operation on the target memory bank based on the memory delay parameter;
wherein the executing a hot-removal operation on the target memory bank comprises:
pulling down a level of a first General Purpose Input/Output (GPIO) pin to remove an address space where the target memory bank is located from an Operating System (OS), so as to set a state of the target memory bank to unavailable.
2. The processing method according to claim 1 , wherein after the executing a hot-addition operation on the target memory bank, the method further comprises:
by the target memory bank, receiving a new read/write command sent by the memory controller, and feeding back a Ready signal to the memory controller after a time delay corresponding to the memory delay parameter, whereby the memory controller executes the read/write operation on the target memory bank after receiving the Ready signal.
3. The processing method according to claim 1 , wherein the executing a hot-addition operation on the target memory bank comprises:
pulling down a level of a second GPIO pin to add the address space where the target memory bank is located to the OS, so as to recover the state of the target memory bank to available.
4. The processing method according to claim 1 , wherein the writing the memory delay parameter into a memory controller comprises:
reading/writing the memory controller through a Platform Environment Control Interface (PECI) bus to write the memory delay parameter into a register of the memory controller.
5. The processing method according to claim 1 , wherein the target memory bank is a Double Data Rate 4 (DDR4) memory bank or a Double Data Rate 3 (DDR3) memory bank.
6. The processing method according to claim 1 , wherein the calculating a memory delay parameter comprises:
acquiring a Memory Reference Code (MRC) in a boot process of a Basic Input/Output System (BIOS), and calculating the memory delay parameter according to the MRC.
7. An electronic device, comprising a storage device and a processor, wherein the storage device stores a computer program, and the processor calls the computer program in the storage device to implement a memory anomaly processing method;
wherein the memory anomaly processing method comprises:
reading a memory error quantity of a target memory bank from a memory error register;
in response to determining that the memory error quantity is greater than a preset value, executing a hot-removal operation on the target memory bank;
calculating a memory delay parameter, and writing the memory delay parameter into a memory controller, wherein the memory delay parameter is waiting time after the memory controller controls the target memory bank to receive a read/write command; and
executing a hot-addition operation on the target memory bank, whereby the memory controller continues to execute a read/write operation on the target memory bank based on the memory delay parameter;
wherein the executing a hot-removal operation on the target memory bank comprises:
pulling down a level of a first General Purpose Input/Output (GPIO) pin to remove an address space where the target memory bank is located from an Operating System (OS), so as to set a state of the target memory bank to unavailable.
8. The electronic device according to claim 7 , wherein after the executing a hot-addition operation on the target memory bank, the method further comprises:
by the target memory bank, receiving a new read/write command sent by the memory controller, and feeding back a Ready signal to the memory controller after a time delay corresponding to the memory delay parameter, whereby the memory controller executes the read/write operation on the target memory bank after receiving the Ready signal.
9. The electronic device according to claim 7 , wherein the executing a hot-addition operation on the target memory bank comprises:
pulling down a level of a second GPIO pin to add the address space where the target memory bank is located to the OS, so as to recover the state of the target memory bank to available.
10. The electronic device according to claim 7 , wherein the writing the memory delay parameter into a memory controller comprises:
reading/writing the memory controller through a Platform Environment Control Interface (PECI) bus to write the memory delay parameter into a register of the memory controller.
11. The electronic device according to claim 7 , wherein the target memory bank is a Double Data Rate 4 (DDR4) memory bank or a Double Data Rate 3 (DDR3) memory bank.
12. The electronic device according to claim 7 , wherein the calculating a memory delay parameter comprises:
acquiring a Memory Reference Code (MRC) in a boot process of a Basic Input/Output System (BIOS), and calculating the memory delay parameter according to the MRC.
13. A non-transitory computer readable storage medium storing computer-executable instructions which when loaded and executed by a processor implement a memory anomaly processing method;
wherein the memory anomaly processing method comprises:
reading a memory error quantity of a target memory bank from a memory error register;
in response to determining that the memory error quantity is greater than a preset value, executing a hot-removal operation on the target memory bank;
calculating a memory delay parameter, and writing the memory delay parameter into a memory controller, wherein the memory delay parameter is waiting time after the memory controller controls the target memory bank to receive a read/write command; and
executing a hot-addition operation on the target memory bank, whereby the memory controller continues to execute a read/write operation on the target memory bank based on the memory delay parameter;
wherein the executing a hot-removal operation on the target memory bank comprises:
pulling down a level of a first General Purpose Input/Output (GPIO) pin to remove an address space where the target memory bank is located from an Operating System (OS), so as to set a state of the target memory bank to unavailable.
14. The non-transitory computer readable storage medium according to claim 13 , wherein after the executing a hot-addition operation on the target memory bank, the method further comprises:
by the target memory bank, receiving a new read/write command sent by the memory controller, and feeding back a Ready signal to the memory controller after a time delay corresponding to the memory delay parameter, whereby the memory controller executes the read/write operation on the target memory bank after receiving the Ready signal.
15. The non-transitory computer readable storage medium according to claim 13 , wherein the executing a hot-addition operation on the target memory bank comprises:
pulling down a level of a second GPIO pin to add the address space where the target memory bank is located to the OS, so as to recover the state of the target memory bank to available.
16. The non-transitory computer readable storage medium according to claim 13 , wherein the writing the memory delay parameter into a memory controller comprises:
reading/writing the memory controller through a Platform Environment Control Interface (PECI) bus to write the memory delay parameter into a register of the memory controller.
17. The non-transitory computer readable storage medium according to claim 13 , wherein the calculating a memory delay parameter comprises:
acquiring a Memory Reference Code (MRC) in a boot process of a Basic Input/Output System (BIOS), and calculating the memory delay parameter according to the MRC.