IP Library Granted Patent US 12,336,406
Granted Patent B2
US 12,336,406 · App. 17/797,352 · Granted Jun 17, 2025

Display

Inventors: Hiromitsu Katsui (Minato-ku, JP); Bo Liu (Gainesville, FL); Maxime Lemaitre (Gainesville, FL)
Assignees: JSR CORPORATION; MATTRIX TECHNOLOGIES, INC.
H10K59/1315H10K50/30H10K59/125
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Quick Facts
Patent No.
US 12,336,406
App. No.
17/797,352
Granted
Jun 17, 2025
Kind
B2
Abstract

A device configuration designed to mitigate display defects resulting from voltage drops in current supply lines offers a display with better display quality. The display includes: a plurality of VOLETs arranged in arrays along a first direction and a second direction; a data line supplying a voltage for controlling gate electrodes of the plurality of VOLETs; TFTs each connected between a gate electrode of each of the VOLET and the data line and controlling voltage supply to the gate electrodes of the VOLETs; a gate line connected to gate electrodes of the TFTs and transmitting a signal that controls the TFTs; a plurality of current supply lines extending along the first direction and supplying a current to each of a group of VOLETs aligned along the first direction; and an auxiliary line extending along the second direction and connecting at least two of the plurality of current supply lines.

Claims (31)

1. A plurality of vertical organic light emitting transistors arranged in arrays along a first direction and a second direction orthogonal to the first direction;

a data line supplying a voltage for controlling gate electrodes of the plurality of vertical organic light emitting transistors;

thin-film transistors each connected between a gate electrode of each of the vertical organic light emitting transistors and the data line and controlling voltage supply to the gate electrodes of the vertical organic light emitting transistors;

a gate line connected to gate electrodes of the thin-film transistors and transmitting a signal that controls the thin-film transistors;

a plurality of current supply lines extending along the first direction and supplying a current to each of a group of vertical organic light emitting transistors aligned along the first direction; and

at least one auxiliary line extending along the second direction and connecting at least two of the plurality of current supply lines;

wherein the at least one auxiliary line includes a wiring line made of a material that makes up the gate line and formed in a layer in which the gate line is provided.

2. The display according to claim 1 , wherein the at least one auxiliary line is formed closer to a substrate than a source electrode of the vertical organic light emitting transistor.

3. The display according to claim 1 , wherein the at least one auxiliary line includes a wiring line made of a material that makes up the gate electrode of the vertical organic light emitting transistor and configured in a layer in which the gate electrode of the vertical organic light emitting transistor is provided.

4. A plurality of vertical organic light emitting transistors arranged in arrays along a first direction and a second direction orthogonal to the first direction;

a data line supplying a voltage for controlling gate electrodes of the plurality of vertical organic light emitting transistors;

thin-film transistors each connected between a gate electrode of each of the vertical organic light emitting transistors and the data line and controlling voltage supply to the gate electrodes of the vertical organic light emitting transistors;

a gate line connected to gate electrodes of the thin-film transistors and transmitting a signal that controls the thin-film transistors;

a plurality of current supply lines extending along the first direction and supplying a current to each of a group of vertical organic light emitting transistors aligned along the first direction; and

at least one auxiliary line extending along the second direction and connecting at least two of the plurality of current supply lines;

wherein the at least one auxiliary line includes a wiring line made of a material that makes up the gate electrode of the vertical organic light emitting transistor and configured in a layer in which the gate electrode of the vertical organic light emitting transistor is provided.

5. The display according to claim 4 , wherein the at least one auxiliary line is formed closer to a substrate than a source electrode of the vertical organic light emitting transistor.

6. A display comprising:

a plurality of vertical organic light emitting transistors arranged in arrays along a first direction and a second direction orthogonal to the first direction;

a data line supplying a voltage for controlling gate electrodes of the plurality of vertical organic light emitting transistors;

thin-film transistors each connected between the gate electrode of each of the vertical organic light emitting transistors and the data line and controlling voltage supply to the gate electrodes of the vertical organic light emitting transistors; and

a gate line connected to the gate electrodes of the thin-film transistors and transmitting a signal that controls the thin-film transistors,

at least two of the plurality of vertical organic light emitting transistors adjacent each other having a source electrode layer continuously formed therebetween.

7. The display according to claim 6 , further comprising a plurality of current supply lines extending along the first direction and supplying a current to each of a group of vertical organic light emitting transistors aligned along the first direction.

8. The display according to claim 7 , further comprising at least one auxiliary line extending along the second direction and connecting at least two of the plurality of current supply lines.

9. The display according to claim 8 , wherein the at least one auxiliary line is formed closer to a substrate than a source electrode of the vertical organic light emitting transistor.

10. The display according to claim 9 , wherein the at least one auxiliary line includes a wiring line made of a material that makes up the gate line and formed in a layer in which the gate line is provided.

11. The display according to claim 10 , wherein the at least one auxiliary line includes a wiring line made of a material that makes up the gate electrode of the vertical organic light emitting transistor and configured in a layer in which the gate electrode of the vertical organic light emitting transistor is provided.

12. The display according to claim 9 , wherein the at least one auxiliary line includes a wiring line made of a material that makes up the gate electrode of the vertical organic light emitting transistor and configured in a layer in which the gate electrode of the vertical organic light emitting transistor is provided.

13. The display according to claim 8 , wherein the at least one auxiliary line includes a wiring line made of a material that makes up the gate line and formed in a layer in which the gate line is provided.

14. The display according to claim 8 , wherein the at least one auxiliary line includes a wiring line made of a material that makes up the gate electrode of the vertical organic light emitting transistor and configured in a layer in which the gate electrode of the vertical organic light emitting transistor is provided.

Assignments (4)
MERGER AND CHANGE OF NAME Recorded Mar 6, 2025
From: JICC-02 CO, LTD.; JSR CORPORATION; JICC-02 CO, LTD.
To: JICC-02 CO, LTD.
Reel/Frame 070427/0597 →
CHANGE OF NAME Recorded Mar 6, 2025
From: JICC-02 CO, LTD.
To: JSR CORPORATION
Reel/Frame 070427/0761 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 16, 2022
From: KATSUI, HIROMITSU
To: JSR CORPORATION
Reel/Frame 061792/0646 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 16, 2022
From: LIU, BO; LEMAITRE, MAXIME
To: MATTRIX TECHNOLOGIES, INC.
Reel/Frame 061792/0696 →
Priority Claims (2)
JP 2020-019527 · Feb 7, 2020 · national
JP 2021-002734 · Jan 12, 2021 · national
Continuity (2)
Provisional Application 63142143 · Jan 27, 2021
Related Publication 20230058493A1 · Feb 23, 2023
References Cited (12)
US 20060103290A1 · Suh et al. · 2006 [cited by applicant]
US 20060202934A1 · Shin et al. · 2006 [cited by applicant]
US 20100244710A1 · Obata et al. · 2010 [cited by applicant]
US 20120074423A1 · Kanegae · 2012 [cited by examiner]
US 20130240842A1 · Rinzler · 2013 [cited by examiner]
CN 107579093A · 2018 [cited by applicant]
JP 2014505324A · 2014 [cited by applicant]
WO 2009036071A2 · 2009 [cited by applicant]
International Search Report for PCT/JP2021/003656 mailed Jul. 13, 2021. [cited by applicant]
Office Action for JP 2021-002734 drafted Jun. 6, 2025 (English translation provided by Applicant). [cited by applicant]
Taiwan Office Action Application No. 110104346 mailed Nov. 26, 2024 (machine translation). [cited by applicant]
CN107579093 published on Jan. 12, 2018 (Translation from Global Dossier Service by EPO). [cited by applicant]