Termination ballast to suppress hotspot formation in trench field plate power MOSFETs
A high voltage trench field plate power MOSFET device is fabricated in a substrate having first and second trenches separated from one another by a narrow epitaxial semiconductor drift pillar structure, where insulated gate electrode layers and insulated field plate layers are formed in the first and second trenches, and where a body well region is formed in an upper portion of the narrow epitaxial semiconductor drift pillar structure to include source contact regions in an active area, and to include an integrated ballast resistor section which connects one or more of the source contact regions to the termination area and which has no source contact regions.
1. A trench field plate power MOSFET device, comprising:
semiconductor substrate structure having a first surface and a second surface;
first and second trenches formed in the first surface of the semiconductor substrate structure and separated from one another by a narrow epitaxial semiconductor drift pillar structure which uniformly separates the first and second trenches and which extends down from the first surface of the semiconductor substrate structure;
a plurality of insulated gate electrode layers formed in upper portions of the first and second trenches to define (1) an active area which includes the plurality of insulated gate electrode layers, and (2) a termination area outside of the active area;
a first insulated field plate layer formed in an upper portion of the first trench that is located outside of the active area;
a second insulated field plate layer formed in a portion of the second trench that is located inside the active area, where the second insulated field plate layer is located below the plurality of insulated gate electrode layers in the active area;
a body well region formed in an upper portion of the narrow epitaxial semiconductor drift pillar structure, the body well region comprising:
a plurality of source contact regions adjacent to the plurality of insulated gate electrode layers, and
an integrated ballast resistor section which connects one or more of the plurality of source contact regions to the termination area and which has no source contact regions; and
a drain region formed on the second surface of the semiconductor substrate structure.
2. The trench field plate power MOSFET device of claim 1 , where the semiconductor substrate structure comprises heavily doped n-type semiconductor substrate layer and a lightly doped n-type epitaxial semiconductor layer in which the first and second trenches are formed to define the narrow epitaxial semiconductor drift pillar structure.
3. The trench field plate power MOSFET device of claim 1 , where the first trench is arrayed on the first surface of the semiconductor substrate structure to surround the second trench, to extend into the termination area, and to substantially align with a subset of the plurality of insulated gate electrode layers in the active area.
4. The trench field plate power MOSFET device of claim 3 , where the second trench comprises a first plurality of parallel trench openings formed in the first surface of the semiconductor substrate structure and connected together on one end with a connecting trench opening, and where the first trench comprises a second plurality of parallel trench openings formed in the first surface of the semiconductor substrate structure to be interspersed with the first plurality of parallel trench openings and connected together on both ends with connecting trench openings to surround the second trench.
5. The trench field plate power MOSFET device of claim 1 , where the body well region comprises a p-type high voltage (PHV) implant well region formed in the narrow epitaxial semiconductor drift pillar structure to uniformly separate the first and second trenches in the active and termination areas.
6. The trench field plate power MOSFET device of claim 5 , where the plurality of source contact regions comprises:
a plurality of N+ source implant regions formed in the PHV implant well region between the plurality of insulated gate electrode layers and within the active area; and
a plurality of P+ implant regions formed in the PHV implant well region in alignment with the plurality of N+ source implant regions but not extending into the termination area.
7. The trench field plate power MOSFET device of claim 1 , where integrated ballast resistor section comprises a predetermined length and/or controlled sheet resistance to produce a positive bias in the body well region to mitigate avalanche hotspots in the trench field plate power MOSFET device.
8. The trench field plate power MOSFET device of claim 2 , where the first trench is arrayed on the first surface of the semiconductor substrate structure to surround the second trench, to extend into the termination area, and to substantially align with a subset of the plurality of insulated gate electrode layers in the active area.
9. The trench field plate power MOSFET device of claim 2 , where the body well region comprises a p-type high voltage (PHV) implant well region formed in the narrow epitaxial semiconductor drift pillar structure to uniformly separate the first and second trenches in the active and termination areas.
10. The trench field plate power MOSFET device of claim 3 , where the body well region comprises a p-type high voltage (PHV) implant well region formed in the narrow epitaxial semiconductor drift pillar structure to uniformly separate the first and second trenches in the active and termination areas.
11. The trench field plate power MOSFET device of claim 2 , where integrated ballast resistor section comprises a predetermined length and/or controlled sheet resistance to produce a positive bias in the body well region to mitigate avalanche hotspots in the trench field plate power MOSFET device.
12. A semiconductor device comprising:
a substrate having first and second substrate surfaces;
a drain formed in the substrate on the second substrate surface;
a first trench formed in the substrate to extend from a top region of the first substrate surface of the semiconductor device to a bottom termination region of the first substrate surface;
a second trench formed in the substrate to surround the first trench and extend to from the top region to the bottom termination region of the first substrate surface;
an epitaxial semiconductor drift pillar structure formed in the substrate to uniformly separate the first and second trenches and extend from the top region to the bottom termination region of the first substrate surface;
a first gate formed in the first trench at the first substrate surface to span a middle region between the top region and the bottom termination region of the first substrate surface;
a second gate formed in the second trench at the first substrate surface to span the middle region between the top region and the bottom termination region of the first substrate surface;
a first partial shield formed in the first trench beneath the first gate to extend between the top region and the bottom termination region of the first substrate surface;
a first full shield formed in the second trench beneath the second gate to surround the first partial shield and to extend between the top region and the bottom termination region of the first substrate surface;
a body well region formed in an upper portion of the epitaxial semiconductor drift pillar structure;
a source formed on the body well region between the first and second gates and in the middle region between the top region and the bottom termination region of the first substrate surface;
one or more source contacts formed on the body well region adjacent to the first gate; and
an integrated ballast resistor formed in the epitaxial semiconductor drift pillar structure to extend from the one or more source contacts to the bottom termination region of the first substrate surface, where the integrated ballast resistor comprises a predetermined length of the body well region having a controlled sheet resistance to produce a positive bias in the body well region to mitigate avalanche hotspots in portions of the epitaxial semiconductor drift pillar structure below the bottom termination region of the first substrate surface,
wherein the source, the first and second gates, and the drain are terminals of a field effect transistor.
13. The semiconductor device of claim 12 , where the source and one or more source contacts are not formed in the predetermined length of the body well region.
14. The semiconductor device of claim 12 , where the one or more source contacts comprise:
one or more first P+ source contacts formed on the body well region adjacent to a first side of the first gate; and
one or more second P+ source contacts formed on the body well region between the first gate and the second gate.
15. The semiconductor device of claim 12 , where the one or more source contacts are P+ source contacts formed on the body well region only between the first gate and the second gate.
16. The semiconductor device of claim 13 , where the one or more source contacts comprise:
one or more first P+ source contacts formed on the body well region adjacent to a first side of the first gate; and
one or more second P+ source contacts formed on the body well region between the first gate and the second gate.
17. The semiconductor device of claim 13 where the one or more source contacts are P+ source contacts formed on the body well region only between the first gate and the second gate.
18. The semiconductor device of claim 14 where the one or more source contacts are P+ source contacts formed on the body well region only between the first gate and the second gate.
19. The semiconductor device of claim 15 where the one or more source contacts are P+ source contacts formed on the body well region only between the first gate and the second gate.