Microelectronic devices, related electronic systems, and methods of forming microelectronic devices

1. A microelectronic device, comprising:

a first microelectronic device structure comprising a memory array region comprising memory cells; and

a second microelectronic device structure vertically overlying the first microelectronic device structure, the second microelectronic device structure comprising:

control logic devices configured to effectuate at least a portion of control operations for the memory cells; and

first multi-capacitor structures within spaces between the control logic devices and horizontally neighboring at least one of the control logic devices, the first multi-capacitor structures spanning a same or fewer number of routing tiers as the control logic devices and configured to regulate and supply voltage to one or more of the control logic devices; and

a third microelectronic device structure vertically overlying the second microelectronic device structure, the third microelectronic device structure comprising second multi-capacitor structures.

2. The microelectronic device of claim 1 , wherein the control logic devices comprise one or more of voltage pumps, delay-locked loop (DLL) circuitry, drain supply voltage (V dd ) regulators, chip/deck control circuitry, block switches, select devices, decoders, repair circuitry, memory test devices, array multiplexers (MUX), error checking and correction (ECC) devices, self-refresh/wear leveling devices, page buffers, data paths, or I/O devices.

3. The microelectronic device of claim 1 , wherein the control logic devices comprise:

two or more routing tiers, each tier having respective routing structures; and

contact structures extending between and contacting at least some of the respective routing structures of the two or more routing tiers.

4. The microelectronic device of claim 3 , wherein the memory array region comprises vertical stacks of dynamic random-access memory (DRAM) cells.

5. The microelectronic device of claim 1 , wherein each of the first multi-capacitor structures comprises a metal-insulator-metal (MIM) capacitor.

6. The microelectronic device of claim 1 , wherein memory array region comprises:

a stack structure comprising:

levels of conductive structures vertically alternating with levels of insulative structures; and

staircase structures at lateral ends of the stack structure; and

vertical stacks of memory cells, at least one of the vertical stacks of memory cells comprising:

stacked capacitor structures, each stacked capacitor structure comprising capacitor structures vertically spaced from each other by at least a level of the levels of insulative structures;

transistor structures, each transistor structure operably coupled to a capacitor structure and to a conductive structure of the levels of conductive structures; and

a conductive pillar structure vertically extending through the transistor structures; and

conductive contact structures in electrical communication with the levels of conductive structures at steps of the staircase structures.

7. The microelectronic device of claim 1 , wherein memory array region comprises one of dynamic random-access memory (DRAM) cells, holographic random-access memory (HRAM) cells, and cross-point memory (MTX) cells.

8. The microelectronic device of claim 1 , further comprising a back end of the line (BEOL) structure over a side of the second microelectronic device structure opposite the first microelectronic device structure.

9. The microelectronic device of claim 1 , wherein the first multi-capacitor structures and the second multi-capacitor structures comprise metal-insulator-metal (MIM) capacitors.