Interference filter and electrostatic discharge / electrical surge protection circuit and device
In some aspects, the techniques described herein relate to an electromagnetic interference (EMI) filter circuit including: an input terminal; an output terminal; an electrical ground terminal; a resistor electrically coupled between the input terminal and the output terminal; a first bipolar transistor including: a collector terminal electrically coupled with the input terminal; an emitter terminal electrically coupled with the electrical ground terminal; and a base terminal that is electrically floating; and a second bipolar transistor including: a collector terminal electrically coupled with the output terminal; an emitter terminal electrically coupled with the electrical ground terminal; and a base terminal that is electrically floating.
1. An electromagnetic interference (EMI) filter circuit comprising:
an input terminal;
an output terminal;
an electrical ground terminal;
a diffusion resistor electrically coupled between the input terminal and the output terminal, the diffusion resistor including at least one diffusion region;
a first bipolar transistor including:
a collector terminal electrically coupled with the input terminal, the collector terminal being included in the at least one diffusion region of the diffusion resistor;
an emitter terminal electrically coupled with the electrical ground terminal; and
a base terminal that is electrically floating; and
a second bipolar transistor including:
a collector terminal electrically coupled with the output terminal;
an emitter terminal electrically coupled with the electrical ground terminal; and
a base terminal that is electrically floating.
2. The EMI filter circuit of claim 1 , wherein the diffusion resistor is a first resistor, the EMI filter circuit further comprising:
a second resistor electrically coupled in series with the first resistor between the input terminal and the output terminal; and
a third bipolar transistor including:
a collector terminal electrically coupled between the first resistor and the second resistor;
an emitter terminal electrically coupled with the electrical ground terminal; and
a base terminal that is electrically floating.
3. The EMI filter circuit of claim 2 , wherein:
the EMI filter circuit is included in a semiconductor device;
the first bipolar transistor is a first vertical bipolar transistor;
the second bipolar transistor is a second vertical bipolar transistor; and
the third bipolar transistor is a third vertical bipolar transistor.
4. The EMI filter circuit of claim 1 , further comprising:
an inductive-capacitive (LC) circuit including:
an inductor; and
a capacitor electrically coupled in parallel with the inductor,
the LC circuit being electrically coupled in series with the diffusion resistor between the input terminal and the output terminal.
5. The EMI filter circuit of claim 4 , wherein the diffusion resistor is a first resistor and the LC circuit is a first LC circuit, the EMI filter circuit further comprising:
a second resistor; and
a second LC circuit,
the first resistor, the first LC circuit, the second LC circuit, and the second resistor being electrically coupled in series between the input terminal and the output terminal, the EMI filter circuit further comprising:
a third bipolar transistor including:
a collector terminal electrically coupled between the first LC circuit and the second LC circuit;
an emitter terminal electrically coupled with the electrical ground terminal; and
a base terminal that is electrically floating.
6. The EMI filter circuit of claim 1 , wherein the diffusion resistor is a first resistor, the EMI filter circuit further comprising:
a second resistor electrically coupled in series with the first resistor between the input terminal and the output terminal.
7. The EMI filter circuit of claim 6 , wherein:
the EMI filter circuit is included in a semiconductor device;
the first bipolar transistor is a first vertical bipolar transistor;
the second bipolar transistor is a second vertical bipolar transistor; and
the second resistor is a second diffusion resistor.
8. A semiconductor device comprising:
a substrate of a first conductivity type;
a semiconductor layer of a second conductivity type that is opposite the first conductivity type;
a first isolation region defined by a first trench;
a first diffusion region of the first conductivity type disposed in the semiconductor layer in the first isolation region;
a second isolation region defined by a second trench;
a second diffusion region of the first conductivity type disposed in the semiconductor layer in the second isolation region;
an electrical ground terminal disposed on the semiconductor layer outside the first isolation region and outside the second isolation region; and
an electromagnetic interference (EMI) filter circuit including:
an input terminal disposed on the semiconductor layer in the first isolation region;
an output terminal disposed on the semiconductor layer in the second isolation region;
a first electrical impedance element disposed in the first isolation region, the first electrical impedance element being a first diffusion resistor included in the first diffusion region;
a second electrical impedance element disposed in the second isolation region, the first electrical impedance element and the second electrical impedance element being electrically coupled in series between the input terminal and the output terminal;
a first vertical bipolar transistor disposed in the first isolation region, the first vertical bipolar transistor including:
a collector terminal electrically coupled with the input terminal, the collector terminal being included in the first diffusion region;
an emitter terminal electrically coupled with the electrical ground terminal; and
a base terminal that is electrically floating; and
a second vertical bipolar transistor disposed in the second isolation region, the second vertical bipolar transistor including:
a collector terminal electrically coupled with the output terminal;
an emitter terminal electrically coupled with the electrical ground terminal; and
a base terminal that is electrically floating.
9. The semiconductor device of claim 8 , wherein:
the first trench extends from an upper surface of the semiconductor layer, through the semiconductor layer and terminates in the substrate, the first trench having a dielectric material disposed therein; and
the second trench extends from the upper surface of the semiconductor layer, through the semiconductor layer and terminates in the substrate, the second trench having the dielectric material disposed therein.
10. The semiconductor device of claim 8 , wherein the electrical ground terminal is electrically coupled with the substrate via a plurality of trenches filled with an electrically conductive material.
11. The semiconductor device of claim 10 , wherein the plurality of trenches filled with the electrically conductive material extend from a surface of the semiconductor layer, through the semiconductor layer and terminate in the substrate.
12. The semiconductor device of claim 8 , wherein:
the second electrical impedance element is a second diffusion resistor included in the second diffusion region.
13. The semiconductor device of claim 12 , wherein:
the base terminal of the first vertical bipolar transistor is included in the semiconductor layer;
the emitter terminal of the first vertical bipolar transistor is included in the substrate;
the collector terminal of the second vertical bipolar transistor is included in the second diffusion region;
the base terminal of the second vertical bipolar transistor is included in the semiconductor layer; and
the emitter terminal of the second vertical bipolar transistor is included in the substrate.
14. The semiconductor device of claim 8 , wherein:
the second electrical impedance element is an inductive-capacitive (LC) circuit.
15. The semiconductor device of claim 8 , wherein the first diffusion region includes:
a first region disposed in the semiconductor layer, the first region having a first doping concentration; and
a second region disposed in the first region, the second region having a second doping concentration that is greater than the first doping concentration.
16. The semiconductor device of claim 8 , wherein:
the first conductivity type is n-type; and
the second conductivity type is p-type.
17. A method comprising:
receiving an electrical transient at one of an input terminal, an output terminal, or an electrical ground terminal of an electromagnetic interference (EMI) filter circuit;
clamping a voltage of the electrical transient with a vertical, open-base bipolar transistor of the EMI filter circuit;
conducting a first portion of a current of the electrical transient with the vertical, open-base bipolar transistor; and
conducting a second portion of the current of the electrical transient with an electrical impedance element of the EMI filter circuit, the second portion of the current being less than the first portion of the current, the electrical impedance element including at least one diffusion region that further includes a collector terminal of the vertical, open-base bipolar transistor,
the collector terminal of the vertical, open-base bipolar transistor being electrically coupled with one of the input terminal or the output terminal,
an emitter terminal of the vertical, open-base bipolar transistor being electrically coupled with the electrical ground terminal, and
the electrical impedance element being electrically coupled between the input terminal and the output terminal.
18. The method of claim 17 , wherein the electrical transient is one of an electrostatic discharge (ESD) or an electrical surge.
19. The method of claim 17 , wherein the electrical impedance element further includes an inductive-capacitive circuit.
20. The method of claim 17 , wherein the vertical, open-base bipolar transistor and the electrical impedance element are included in an isolation region of the EMI filter circuit.