Image sensor synchronization without input clock and data transmission clock
The disclosure extends to systems and methods for reducing the area of an image sensor by reducing the imaging sensor pad count used for data transmission and clock generation.
1. An endoscopic system for use in a light deficient environment comprising:
an endoscope comprising an image sensor, wherein the image sensor comprises a plurality of bidirectional data pads;
a control circuit in electronic communication with the image sensor;
wherein electronic communication through each of the bidirectional data pads is performed in a frame period, wherein the frame period is defined in four phases comprising:
a first phase where non-pixel data is issued from the image sensor through the bidirectional data pads;
a second phase during which internal timing signals, synchronization data, and readout of pixel data is output from the image sensor through the bidirectional data pads;
a third phase where non-pixel data is issued from the image sensor through the bidirectional data pads; and
a fourth phase during which image sensor configuration data and commands are received by the image sensor through the bidirectional data pads;
wherein clock signal data is transmitted during the first phase, the third phase, and the fourth phase of the frame period, but not during the second phase when pixel data is readout.
2. The endoscopic system of claim 1 , wherein at startup the electronic communication through each of the bidirectional data pads is performed in a plurality of frame periods, wherein the first phase, the second phase, and the third phase are merged in a continuous period of clock training in each of the plurality of frames; and
a clock training period in which at least the rolling-readout phase and the service-line phase are combined into a continuous period of clock training in which non-image data is output from the image sensor through the bidirectional data pads to the control circuit.
3. The endoscopic system of claim 1 , wherein the control circuit comprises a clock data recovery (CDR) system that latches the incoming data from the first phase, the second phase, and the third phase of the frame period of the image sensor, thereby eliminating the need for dedicated clock data pads.
4. The endoscopic system of claim 3 , wherein the clock data recovery (CDR) system comprises a phase locked loop to lock the incoming data frequency and to latch the incoming data.
5. The endoscopic system of claim 4 , wherein the locking process requires data transitions for the phase locked loop to converge, wherein a minimum number of transitions is specified for locking and re-locking along with a maximum number of consecutive allowed bits without transition is specified.
6. The endoscopic system of claim 1 , wherein the non-pixel data issued from the image sensor comprises signal transitions as service lines within frame data.
7. The endoscopic system of claim 6 , wherein signal transitions are encoded within output data from the image sensor that correspond to the defined phases of the bidirectional data pads; and
wherein signal transitions are encoded within pixel data that is output from the image sensor in correspondence to the defined phases of the bidirectional data pads by adding an additional bit to the pixel data, where the additional bit is an inverted version of a specified bit out of a plurality of bits in the pixel data.
8. The endoscopic system of claim 1 , wherein a camera unit clock is used to synchronize incoming sensor data.
9. The endoscopic system of claim 1 , wherein a data recovery circuit is used to lock on incoming sensor data to keep it synchronized.
10. The endoscopic system of claim 1 , further comprising at least one transition within each of a plurality of pixel data values created within a pixel array of the image sensor.
11. The endoscopic system of claim 10 , further comprising one or more transitions during a series of the plurality of pixel data values created by the pixel array.
12. The endoscopic system of claim 1 , wherein pixel data in at least one pixel data value is replaced with clock signal data for synchronization.
13. The endoscopic system of claim 1 , wherein pixel data in at least one pixel data value is replaced with clock signal data within at least one phase of one frame period.
14. The endoscopic system of claim 1 , wherein pixel data in at least one pixel data value is replaced with clock signal data within the first phase just prior to the second phase where pixel data is readout and output from the image sensor to the control circuit.
15. The endoscopic system of claim 1 , further comprising a phase lock loop built with blocks of the image sensor and blocks of the camera unit;
wherein the system further comprises data lines and configuration lines electrically connecting image sensor phase lock loop blocks and camera unit phase lock loop blocks together; and
wherein a camera unit clock and a data recovery circuit are used to lock on to incoming sensor data.
16. The endoscopic system of claim 1 , wherein the bidirectional data pads are configured to reverse direction and receive commands from external system components during the fourth phase of the frame period while in receive mode.
17. The endoscopic system of claim 1 , further comprising a phase lock loop based on one or more of a charge pump and a digital to analog convertor for driving a voltage controlled oscillator.
18. The endoscopic system of claim 1 , further comprising a sensor configuration register configured to store changes to an operating frequency.
19. The endoscopic system of claim 1 , further comprising a local oscillator as a phase lock loop reference clock.
20. An endoscopic system for use in a light deficient environment comprising:
an endoscope comprising an image sensor, wherein the image sensor comprises a plurality of bidirectional data pads;
a control circuit in electronic communication with the image sensor;
wherein electronic communication through each of the bidirectional data pads is performed in a frame period, wherein the frame period is defined in four phases comprising:
a first phase where non-pixel data is issued from the image sensor through the bidirectional data pads;
a second phase during which internal timing signals, synchronization data, and readout of pixel data is output from the image sensor through the bidirectional data pads;
a third phase where non-pixel data is issued from the image sensor through the bidirectional data pads; and
a fourth phase during which image sensor configuration data and commands are received by the image sensor through the bidirectional data pads;
wherein the control circuit comprises a phase locked loop to lock an incoming data frequency;
wherein the locking the incoming data requires data transitions for the phase locked loop to converge, wherein a minimum number of transitions is specified for locking and re-locking along with a maximum number of consecutive allowed bits without transition is specified.