Semiconductor layer structure

1. A semiconductor layer structure comprising:

a Si substrate having a top surface;

a first semiconductor layer arranged on said substrate, the first semiconductor layer comprising a plurality of vertical nanowire structures arranged perpendicularly to said top surface of said substrate, the first semiconductor layer comprising AlN;

a second semiconductor layer arranged on said first semiconductor layer laterally and vertically enclosing said nanowire structures, the second semiconductor layer comprising AlxGa1-xN, wherein 0≤x≤0.95, the second semiconductor layer comprising at least two dislocations, each of the two dislocations propagating laterally from separate nanowire structures in an M-direction of a wurtzite crystal structure, the two dislocations being coalesced with each other;

a third semiconductor layer arranged on said second semiconductor layer, the third semiconductor layer comprising AlyGa1-yN, wherein 0≤y≤0.95; and

a fourth semiconductor layer arranged on said third semiconductor layer, the fourth semiconductor layer comprising GaN.

2. The semiconductor layer structure according to claim 1 , further comprising a bottom semiconductor layer, arranged intermediate to the top surface of the substrate and the first semiconductor layer, the bottom semiconductor layer comprising AlN.

3. The semiconductor layer structure according to claim 2 , further comprising an intermediate semiconductor layer, arranged intermediate to the bottom semiconductor layer and the first semiconductor layer, the intermediate semiconductor layer comprising AlN.

4. The semiconductor layer structure according to claim 1 , wherein the top surface of the Si substrate has a Miller index of {111}.

5. The semiconductor layer structure according to claim 1 , wherein said fourth semiconductor layer has a vertical thickness in the range 1-5 nm.

6. The semiconductor layer structure according to claim 1 , wherein the second semiconductor layer comprises at least two vertically arranged sublayers, wherein x for a first sublayer is greater than x for a second sublayer, wherein the second sublayer is located further from the substrate than the first sublayer.

7. A high-electron-mobility transistor device comprising:

the semiconductor layer structure according to claim 1 ;

a metallic source contact arranged directly adjacent to the second semiconductor layer;

a metallic drain contact arranged directly adjacent to the second semiconductor layer, wherein the drain contact is separate from the source contact; and

a metallic gate contact arranged on the fourth semiconductor layer, wherein the gate contact is arranged laterally between the source and drain contacts, and wherein the gate contact is separate from the source and drain contacts.

8. The high-electron-mobility transistor device according to claim 7 , wherein the fourth semiconductor layer is arranged as a vertical fin, wherein the vertical fin is arranged directly adjacent to the third semiconductor layer, wherein the gate contact is arranged to laterally and vertically enclose the vertical fin, and wherein the vertical fin comprises p-doped GaN.

9. A method for producing a semiconductor layer structure, the method comprising:

providing a Si substrate comprising a top surface;

forming a first semiconductor layer on said substrate, the first semiconductor layer comprising a plurality of vertical nanowire structures, arranged perpendicularly to said top surface of said substrate, the first semiconductor layer comprising AlN;

depositing a second semiconductor layer on the first semiconductor layer, laterally and vertically enclosing said nanowire structures, wherein the second semiconductor layer comprises AlxGa1-xN, wherein 0≤x≤0.95, the second semiconductor layer comprising at least two dislocations, each of the two dislocations propagating laterally from separate nanowire structures in an M-direction of a wurtzite crystal structure, the two dislocations being coalesced with each other;

depositing a third semiconductor layer on said second semiconductor layer, the third semiconductor layer comprising AlyGa1-yN, wherein 0≤y≤0.95; and

depositing a fourth semiconductor layer on said third semiconductor layer, the fourth semiconductor layer comprising GaN.

10. The method according to claim 9 , wherein forming said first semiconductor layer comprises:

depositing the first semiconductor layer on the substrate; and

etching the plurality of vertical nanowire structures from the first semiconductor layer.

11. The method according to claim 9 , wherein forming said first semiconductor layer comprises epitaxially forming the plurality of vertical nanowire structures on the substrate.

12. The method according to claim 9 , further comprising depositing a bottom semiconductor layer intermediate to providing the substrate and forming the first semiconductor layer, the bottom semiconductor layer comprising AlN.

13. The method according to claim 12 , further comprising depositing an intermediate semiconductor layer intermediate to depositing the bottom semiconductor layer and forming the first semiconductor layer, the intermediate semiconductor layer comprising AlN.

14. The method according to claim 9 , wherein forming said second semiconductor layer comprises:

forming a first sublayer on the first semiconductor layer; and

forming a second sublayer on the first sublayer, wherein x for the first sublayer is greater than x for the second sublayer.

15. A method for producing a high-electron-mobility transistor device, the method comprising:

the steps of the method for producing a semiconductor layer structure according to claim 9 ;

forming at least two trenches through the third and fourth semiconductor layers by etching away portions of said third and fourth semiconductor layers;

depositing a first metallic layer into the trenches and on the second semiconductor layer;

forming a metallic source contact and a metallic drain contact, in the trenches, by etching away portions of the first metallic layer;

forming an oxide layer on the source and drain contacts;

forming a gate trench through the oxide layer, between and separate from the at least two trenches through the third and fourth semiconductor layers, by etching away a portion of the oxide layer;

depositing a second metallic layer into the gate trench; and

forming a metallic gate contact, in the gate trench, by etching away portions of the second metallic layer.