Wide input voltage range low-power charge pump based LDO

1. A low-dropout linear regulator comprising:

a voltage-to-frequency circuit including a first input receiving a reference voltage, a second input, and an output providing a pulse chain at a frequency related to a voltage difference between the first and second inputs;

a charge pump circuit receiving the pulse chain and switching one or more charge pumps based on the pulse chain to provide a charge pump output voltage; and

a current mirror circuit including:

a first metal-oxide semiconductor (MOS) transistor having a first terminal coupled to a supply voltage through a resistor, a second terminal connected to the charge pump output voltage, and a gate connected to the second terminal; and

a second MOS transistor having a first terminal connected to the supply voltage, a second terminal providing an output connected to a positive terminal of an output capacitor and to the second input of the voltage-to-frequency circuit, and a gate connected to the gate of the first MOS transistor.

2. The low-dropout linear regulator of claim 1 , wherein the voltage-to-frequency circuit comprises:

a comparator having first and second inputs connected to the first and second voltage-to-frequency circuit inputs, a reset input, and an output; and

a pulse generator for providing the pulse chain, including an input connected to the output of the comparator, and an output providing the pulse chain, the output connected to the reset input of the comparator.

3. The driver circuit of claim 2 , wherein:

the charge pump circuit includes a plurality of charge pumps, each including an enable input coupled to a controller for selectively activating and deactivating the charge pumps to adjust a gain of the low dropout linear regulator.

4. The low-dropout linear regulator of claim 3 , further comprising:

a control circuit having a plurality of control outputs coupled to respective enable inputs of the charge pumps for controlling how many charge pumps are activated during operation of the low-dropout linear regulator.

5. The low-dropout linear regulator of claim 4 , wherein:

the control circuit has an input connected to the output capacitor for monitoring the output voltage of the low-dropout linear regulator.

6. The low-dropout linear regulator of claim 1 , wherein the one or more charge pumps each comprise:

an inverter having an input receiving the pulse chain and an output;

a first p-type metal oxide semiconductor (PMOS) transistor with a source connected to the supply voltage, a drain coupled to the inverter input through a first capacitor, and a gate coupled to the inverter output through a second capacitor;

a first n-type metal oxide semiconductor (NMOS) transistor with a drain connected to the drain of the first PMOS transistor, a source connected to a charge pump output, and a gate connected to the gate of the first PMOS transistor;

a second PMOS transistor with a source connected to the supply voltage, a drain coupled to the inverter output through the second capacitor, and a gate connected to the drain of the first PMOS transistor; and

a second NMOS transistor with a drain connected to the drain of the second PMOS transistor, a source connected to the charge pump output, and a gate connected to the gate of the second PMOS transistor.

7. The driver circuit of claim 1 , wherein:

the first and second MOS transistors are laterally-diffused metal-oxide semiconductor (LDMOS) transistors.

8. A method of providing a low-drop out regulated voltage, comprising:

producing a pulse chain at a variable frequency related to a voltage difference between a regulated voltage and a reference voltage;

driving a charge pump circuit with the pulse chain to provide a charge pump output voltage; and

feeding the charge pump output voltage to gates of MOS transistors in a current mirror circuit including a first MOS transistor with a first terminal connected to its gate and a second terminal coupled to a supply voltage through a resistor, and a second MOS transistor coupled between the supply voltage and an output capacitor.

9. The method of claim 8 , wherein producing the pulse chain further comprises:

comparing the regulated voltage and a reference voltage with a comparator;

generating a pulse based on the regulated voltage being lower than the reference voltage; and

resetting the comparator with the pulse.

10. The method of claim 8 , wherein:

the charge pump circuit includes a plurality of charge pumps connected in parallel.

11. The method of claim 8 , further comprising:

selectively disabling some of the plurality of charge pumps while producing the regulated voltage.

12. The method of claim 8 , wherein:

the first and second MOS transistors are laterally-diffused metal-oxide semiconductor (LDMOS) transistors.

13. An integrated circuit comprising:

a low-dropout linear regulator comprising:

a voltage-to-frequency circuit including a first input receiving a reference voltage, a second input, and an output providing a pulse chain at a frequency related to a voltage difference between the first and second inputs;

a charge pump circuit receiving the pulse chain and switching one or more charge pumps based on the pulse chain to provide a charge pump output voltage; and

a current mirror circuit including:

a first metal-oxide semiconductor (MOS) transistor having a first terminal coupled to a supply voltage through a resistor, a second terminal connected to the charge pump output voltage, and a gate connected to the second terminal; and

a second MOS transistor having a first terminal connected to the supply voltage, a second terminal providing an output connected to a positive terminal of an output capacitor and to the second input of the voltage-to-frequency circuit, and a gate connected to the gate of the first LDMOS transistor.

14. The integrated circuit of claim 13 , wherein the voltage-to-frequency circuit comprises:

a comparator having first and second inputs connected voltage-to-frequency circuit inputs, a reset input, and an output; and

a pulse generator for providing the pulse chain, including an input connected to the output of the comparator, and an output providing the pulse chain, the output connected to the reset input of the comparator.

15. The integrated circuit of claim 14 , wherein:

the charge pump circuit includes a plurality of charge pumps, each including an enable input coupled to a controller for selectively activating and deactivating the charge pumps to adjust a gain of the low dropout linear regulator.

16. The integrated circuit of claim 15 , further comprising:

a control circuit having a plurality of control outputs coupled to respective enable inputs of the charge pumps for controlling how many charge pumps are activated during operation of the low-dropout linear regulator.

17. The integrated circuit of claim 16 , wherein:

the control circuit has an input connected to the output capacitor for monitoring the output voltage of the low-dropout linear regulator.

18. The integrated circuit of claim 13 , wherein the one or more charge pumps each comprise:

an inverter having an input receiving the pulse chain and an output;

a first p-type metal oxide semiconductor (PMOS) transistor with a source connected to the supply voltage, a drain coupled to the inverter input through a first capacitor, and a gate coupled to the inverter output through a second capacitor;

a first n-type metal oxide semiconductor (NMOS) transistor with a drain connected to the drain of the first PMOS transistor, a source connected to the charge pump output, and a gate connected to the gate of the first PMOS transistor;

a second PMOS transistor with a source connected to the supply voltage, a drain coupled to the inverter output through the second capacitor, and a gate connected to the drain of the first PMOS transistor; and

a second NMOS transistor with a drain connected to the drain of the second PMOS transistor, a source connected to the charge pump output, and a gate connected to the gate of the second PMOS transistor.

19. The integrated circuit of claim 13 , wherein:

the first and second MOS transistors are laterally-diffused metal-oxide semiconductor (LDMOS) transistors.