Antenna port termination in absence of power supply
Methods and devices to address antenna termination in absence of power supplies within an electronic circuit including a termination circuit and a switching circuit. The devices include regular NMOS devices that decouple the antenna from the switching circuit in absence of power supplies while the antenna is coupled to a terminating impedance having a desired impedance value through a native NMOS device. The antenna is coupled with the switching circuit via the regular NMOS device during powered conditions while the antenna is decoupled from the terminating impedance.
1. An electronic circuit, comprising:
an RF switching circuit having a plurality of single-pole single-throw switches, each single-pole single-throw switch comprising one or more RF switching circuit transistors;
a termination circuit coupled between an antenna node and a ground node, the termination circuit comprising a termination impedance coupled to the ground node and a first switch connected in series with the termination impedance, the first switch comprising one or more termination circuit transistors having a first threshold voltage;
a second switch connected between the termination circuit and the RF switching circuit, the second switch comprising one or more second switch transistors having a second threshold voltage;
wherein the second threshold voltage is greater than the first threshold voltage.
2. The electronic circuit of claim 1 , wherein the electronic circuit has a powered state in which one or more supply voltages are connected to the electronic circuit and an unpowered state in which some or all of the supply voltages have been disconnected from the electronic circuit.
3. The electronic circuit of claim 1 , wherein the electronic circuit has a powered state in which a supply voltage is connected to the first switch and the second switch and an unpowered state in which the supply voltage has been disconnected from the first switch and the second switch.
4. The electronic circuit of claim 3 , wherein the first and the second threshold voltages are such that:
i) in the powered state of the electronic circuit:
the first switch is in an OFF state;
the second switch is in an ON state; and
the termination circuit is connected to the RF switching circuit; and
ii) in the unpowered state of the electronic circuit:
the first switch is in an ON state;
the second switch is in an OFF state; and
the RF switching circuit is disconnected from the termination circuit.
5. The electronic circuit of claim 3 , wherein the first and the second threshold voltages are such that:
i) in the powered state of the electronic circuit:
the first switch is in an open circuit state;
the second switch is in a closed circuit state; and
the termination circuit is connected to the RF switching circuit; and
ii) in the unpowered state of the electronic circuit:
the first switch is in a closed circuit state;
the second switch is in an open circuit state; and
the RF switching circuit is disconnected from the termination circuit.
6. The electronic circuit of claim 5 , wherein the first switch comprises a stack of two or more serially connected transistors.
7. The electronic circuit of claim 6 , wherein the second switch comprises a stack of two more serially connected transistors.
8. The electronic circuit of claim 1 , wherein in a powered state of the electronic circuit, the first switch receives a first supply voltage and the second switch receives a second supply voltage different from the first supply voltage, and wherein in an unpowered state of the electronic circuit, the first and the second switches receive zero bias voltages.
9. The electronic circuit of claim 8 , wherein, in the powered state of the electronic circuit, the first supply voltage is negative and the second supply voltage is positive.
10. The electronic circuit of claim 1 , wherein the first switch comprises one or more native NMOS transistors and the second switch comprises one or more regular NMOS transistors.
11. The electronic circuit of claim 1 , wherein the plurality of single-pole single-throw switches comprise a through switch.
12. The electronic circuit of claim 11 , wherein the plurality of single-pole single-throw switches comprise a shunt switch.
13. The electronic circuit of claim 12 , wherein the shunt switch comprises a shunt switch stack comprising a plurality of native NMOS serially connected transistors.
14. The electronic circuit of claim 11 , wherein the through switch comprises a through switch stack comprising a plurality of native NMOS serially connected transistors.