Data preprocessing (DPP) pattern supporting both normal program and early cache release program (ECRP)

1. A memory device comprising:

N data latches configured to store data, wherein N is a positive integer; and

a controller coupled to the N data latches and configured to:

receive data that includes data units, wherein each of the data units includes N bits;

store the data units in the N data latches;

convert the data units based on a first table and a second table; and

program cells of the memory device based on the converted data units,

wherein the first and the second tables include N rows and 2 N columns of bits;

wherein bits from column 2 N-1 +2 to column 2 N in N th row of the second table are identical;

wherein L th column of the second table contains K number of “0” in one or more rows of the L th column,

wherein one or more rows of M th column of the second table contain less than K number of 0,

wherein L, K, and M are positive integers, and

wherein L is less than M.

2. The memory device of claim 1 , wherein to convert the data units, the controller is further configured to:

determine that a data unit of the data units matches bits of I th column of the first table, where I is a positive integer; and

convert the data unit to bits of I th column of the second table.

3. The memory device of claim 1 , wherein columns of the second table correspond to a set of respective voltage levels.

4. The memory device of claim 1 , wherein to store the data units in the N data latches, the controller is further configured to:

store J th bit of each of the data units in J th data latch,

wherein J is a positive integer.

5. The memory device of claim 1 , wherein to program the cells of the memory device based on the converted data units, the controller is further configured to:

determine that one or more data units of the converted data units match a target column of the second table;

determine a target voltage level corresponding to the target column;

determine one or more cells of the cells of the memory device corresponding to the one or more data units; and

program the one or more cells to the target voltage level.

6. The memory device of claim 5 , wherein the controller is further configured to verify the one or more cells, the controller is configured to:

determine that a set of rows of the target column of the second table contains “0” bits;

determine the one or more data units based on the set of rows;

determine the one or more cells based on the one or more data units;

verify that voltage levels of the one or more cells are higher than a voltage requirement; and

convert one or more rows of the one or more data units to “1” bits based on the set of rows.

7. The memory device of claim 6 , wherein the controller is further configured to:

determine that the target column is column 2 N-1 +1 of the second table; and

release N th data latch of the memory device.

8. A method for operating a memory device, comprising:

receiving data that includes data units, wherein each of the data units includes N bits wherein N is a positive integer;

storing the data units in N data latches;

converting the data units based on a first table and a second table; and

programing cells of the memory device based on the converted data units,

wherein the first and the second tables include N rows and 2 N columns of bits;

wherein bits from column 2 N-1 +2 to column 2 N N th row of the second table are identical;

wherein L th column of the second table contains K number of “0” in one or more rows of the L th column,

wherein the one or more rows of M th column of the second table contain less than K number of 0,

wherein L, K, and M are positive integers, and

wherein L is less than M.

9. The method of claim 8 , wherein the converting the data units further comprises:

determining that a data unit of the data units matches bits of I th column of the first table; and

converting the data unit to bits of I th column of the second table,

wherein I is a positive integer.

10. The method of claim 8 , wherein columns of the second table correspond to respective a set of voltage levels.

11. The method of claim 8 , wherein the storing the data units in the N data latches further comprises:

storing J th bit of each of the data units in J th data latch,

wherein J is a positive integer.

12. The method of claim 8 , wherein the programing the cells of the memory device based on the converted data units further comprises:

determining that one or more data units of the converted data units match a target column of the second table;

determining a target voltage level corresponding to the target column;

determining one or more cells of the cells of the memory device corresponding to the one or more data units; and

programing the one or more cell to the target voltage level.

13. The method of claim 12 , further comprising verifying the one or more cells by:

determining that a set of rows of the target column of the second table contain “0” bits;

determining the one or more data units based on the set of rows;

determining the one or more cells based on the one or more data units;

verifying that voltage levels of the one or more cells are higher than a voltage requirement; and

converting one or more rows of the one or more data units to “1” bits based on the set of rows.

14. The method of claim 13 , further comprising:

determining that the target column is column 2 N-1 +1 of the second table; and

releasing N th data latch of the memory device.

15. A non-transitory computer-readable medium (CRM) comprising instructions to, upon execution of the instructions by one or more processors of a memory device, cause the memory device to perform operations, the operations comprising:

receiving data that includes data units, wherein each of the data units includes N bits, wherein N is a positive integer;

storing the data units in N data latches;

converting the data units based on a first table and a second table; and

programing cells of the memory device based on the converted data units,

wherein the first and the second tables include N rows and 2 N columns of bits;

wherein bits from column 2 N-1 +2 to column 2 N in N th row of the second table are identical;

wherein L th column of the second table contains K number of “0” in one or more rows of the L th column,

wherein the one or more rows of M th column of the second table contain less than K number of 0,

wherein L, K, and M are positive integers, and

wherein L is less than M.

16. The non-transitory CRM of claim 15 , wherein the converting the data units further comprises:

determining that a data unit of the data units matches bits of I th column of the first table; and

converting the data unit to bits of I th column of the second table,

wherein I is a positive integer.

17. The non-transitory CRM of claim 15 , wherein the storing the data units in the N data latches further comprises:

storing J th bit of each of the data units in J th data latch,

wherein J is a positive integer.

18. The non-transitory CRM of claim 15 , wherein the programing the cells of the memory device based on the converted data units further comprises:

determining that one or more data units of the converted data units match a target column of the second table;

determining a target voltage level corresponding to the target column;

determining one or more cells of the cells of the memory device corresponding to the one or more data units; and

program the one or more cells to the target voltage level.

19. The non-transitory CRM of claim 18 , wherein the operations further comprise verifying the one or more cells by:

determining that a set of rows of the target column of the second table contain “0” bits;

determining the one or more data units based on the set of rows;

determining the one or more cells based on the one or more data units;

verifying that voltage levels of the one or more cells are higher than a threshold; and

converting one or more rows of the one or more data units to “1” bits based on the set of rows.

20. The non-transitory CRM of claim 19 , wherein the operations further comprise:

determining that the target column is column 2 N-1 +1 of the second table; and

releasing N th data latch of the memory device.