Substrate alignment systems and related methods
Implementations of a method of making a plurality of alignment marks on a wafer may include: providing a wafer including an alignment feature on a first side of the wafer. The method may include aligning the wafer using a camera focused on the first side of the wafer. The wafer may be aligned using the alignment feature on the first side of the die. The wafer may also include creating a plurality of alignment marks on a second side of the wafer through lasering, sawing, or scribing.
1. A wafer comprising:
a first side and a second side opposite the first side;
an alignment feature on the first side of the wafer;
a metal layer comprised on the second side of the wafer;
a plurality of alignment marks extending only partially into a thickness of the metal layer;
a patterned metal layer directly coupled to the first side of the wafer; and
a passivation layer directly coupled to the first side of the wafer and also coupled over the patterned metal layer;
wherein the metal layer is a backside metal layer; and
wherein an entire surface of the metal layer directly coupled to the second side of the wafer is continuous and lies in a single plane.
2. The wafer of claim 1 , wherein the wafer comprises a thickness of 50 microns or less.
3. The wafer of claim 1 , wherein the plurality of alignment marks correspond with the plurality of alignment features.
4. The wafer of claim 1 , further comprising a ring formed around a perimeter of the second side of the wafer.
5. The wafer of claim 1 , wherein the metal layer covers an entire semiconductor device comprised in the wafer.
6. A wafer comprising:
a first side and a second side opposite the first side, wherein the first side comprises an active surface;
an alignment feature in a die street on the first side of the wafer between a plurality of active areas on the first side of the wafer;
a metal layer comprised on the second side of the wafer, wherein an entirety of a surface of the metal layer directly coupled to the wafer lies in a single plane; and
a plurality of alignment marks comprised in a thickness of the metal layer;
wherein the wafer comprises a thickness of 50 microns or less; and
wherein the metal layer comprises a thickness of 10 microns or less.
7. The wafer of claim 6 , wherein the plurality of alignment marks extend only partially through a thickness of the metal layer.
8. The wafer of claim 6 , further comprising a passivation layer directly coupled to the first side of the die.
9. The wafer of claim 6 , wherein the plurality of alignment marks correspond with the plurality of alignment features.
10. The wafer of claim 6 , further comprising a ring formed around a perimeter of the second side of the wafer.
11. The wafer of claim 6 , wherein the metal layer covers an entire semiconductor device comprised in the wafer.
12. A wafer comprising:
a first side and a second side opposite the first side;
a plurality of die and one or more die streets between each of the plurality of die;
a plurality of alignment features in the one or more die streets on the first side of the wafer between a plurality of active areas on the first side of the wafer;
a metal layer comprised on the second side of the wafer;
a second metal layer comprised on the first side of the wafer;
a passivation layer directly coupled to and over the first side of the wafer and the second metal layer; and
a plurality of alignment marks comprised in a thickness of the metal layer;
wherein the plurality of alignment marks correspond with one or more of the plurality of alignment features; and
wherein an entirety of a surface of the metal layer directly coupled to the wafer lies in a single plane.
13. The wafer of claim 12 , wherein the metal layer is a backside metal layer.
14. The wafer of claim 12 , wherein the plurality of alignment marks extends only partially through a thickness of the metal layer.
15. The wafer of claim 12 , wherein the wafer comprises a thickness of 50 microns or less.
16. The wafer of claim 12 , further comprising a third metal layer directly coupled to the second metal layer, wherein the passivation layer is directly coupled to both the second metal layer and the third metal layer.
17. The wafer of claim 12 , wherein the metal layer covers an entire semiconductor device comprised in the wafer.