Advanced initialization bus (AIB)
Methods and systems for an advanced initialization bus (AIB) are presented. In an aspect, an AIB master sends, to an AIB slave, a serial clock over a first signal line, and performs a read operation with the AIB slave. Performing the read operation comprises sending a read command to the AIB slave via a bus comprising at least one bidirectional input/output (I/O) channel, each I/O channel having its own respective signal line, sending a read address to the AIB slave via the bus, receiving a copy of the serial clock from the AIB slave over a second signal line, and latching read data provided by the AIB slave via the bus into a read buffer using the copy of the serial clock as a data strobe. Thus, the AIB master latches the read data provided by the AIB slave using a read strobe also provided by the AIB slave.
1. A method, performed by a bus master of a serial bus, the method comprising:
sending, to a bus slave, a first serial clock over a first signal line; and
performing a bus operation with the bus slave, the bus operation comprising a read operation or a write operation;
wherein performing the read operation comprises:
sending a read command and a read address to the bus slave via a bus comprising at least one bidirectional input/output (I/O) channel, each I/O channel having its own respective signal line, wherein the read command and the read address are substantially edge aligned with one of a rising edge or a falling edge of the first serial clock and substantially center aligned with the other of the rising edge or the falling edge of the first serial clock;
receiving a second serial clock from the bus slave over a second signal line;
latching read data provided by the bus slave via the bus into an asynchronous, first-in, first-out (AFIFO) buffer using the second serial clock as a data strobe, wherein the read data is substantially edge aligned with one of a rising edge or a falling edge of the second serial clock and substantially center aligned with the other of the rising edge or the falling edge of the second serial clock; and
reading the read data from the AFIFO buffer using a master clock, the master clock comprising a third serial clock that is distinct from the first serial clock and the second serial clock.
2. The method of claim 1 , wherein the bus comprises four bidirectional I/O channels.
3. The method of claim 1 , wherein performing the write operation comprises:
sending a write command to the bus slave via the bus;
sending a write address to the bus slave via the bus; and
sending write data to the bus slave via the bus.
4. The method of claim 3 , further comprising, after sending the write address, and before sending the write data, asserting and later releasing a wait state, via the second signal line.
5. A method, performed by a bus slave of a serial bus, the method comprising:
receiving, from a bus master, a first serial clock over a first signal line; and
performing a bus operation with the bus master, the bus operation comprising a read operation or a write operation;
wherein performing the read operation comprises:
receiving a read command and a read address from the bus master via a bus comprising at least one bidirectional input/output (I/O) channel, each I/O channel having its own respective signal line, wherein the read command and the read address are substantially edge aligned with one of a rising edge or a falling edge of the first serial clock and substantially center aligned with the other of the rising edge or the falling edge of the first serial clock;
sending read data to the bus master via the bus according to the serial clock; and
sending a second serial clock to the bus master over a second signal line for use by the bus master as a data strobe, wherein the read data is substantially edge aligned with one of a rising edge or a falling edge of the second serial clock and substantially center aligned with the other of the rising edge or the falling edge of the second serial clock.
6. The method of claim 5 , wherein the bus comprises four bidirectional I/O channels.
7. The method of claim 5 , further comprising, after receiving the read address and before sending the read data, asserting a wait state, during which the second serial clock is not sent to the bus master over the second signal line.
8. The method of claim 5 , wherein performing the write operation comprises:
receiving a write command from the bus master via the bus;
receiving a write address from the bus master via the bus; and
receiving write data from the bus master via the bus.
9. The method of claim 8 , further comprising, after receiving the write address, and before receiving the write data, detecting assertion and later release of a wait state by the bus master, via the second signal line.
10. An apparatus for operating as a bus master of a serial bus, the apparatus comprising:
a controller circuit; and
at least one input, output, or input/output port;
wherein the controller circuit is configured to perform a bus operation with a bus slave, the bus operation comprising a read operation or a write operation;
wherein, to perform the read operation, the controller circuit is configured to:
send a first serial clock to the bus slave over a first signal line;
send a read command and a read address to the bus slave via a bus comprising at least one bidirectional input/output (PO) channel, each I/O channel having its own respective signal line, wherein the read command and the read address are substantially edge aligned with one of a rising edge or a falling edge of the first serial clock and substantially center aligned with the other of the rising edge or the falling edge of the first serial clock;
receive a second serial clock from the bus slave over a second signal line;
latch read data provided by the bus slave via the bus into an asynchronous first-in, first-out (AFIFO) buffer using the second serial clock as a data strobe, wherein the read data is edge aligned with one of a rising edge or a falling edge of the second serial clock and center aligned with the other of the rising edge or the falling edge of the second serial clock; and
read the read data from the AFIFO buffer using a master clock, the master clock comprising a third serial clock that is distinct from the first serial clock and the second serial clock.
11. The apparatus of claim 10 , wherein the bus comprises four bidirectional I/O channels.
12. The apparatus of claim 10 , wherein, to perform the write operation, the controller circuit is configured to:
send a write command to the bus slave via the bus;
send a write address to the bus slave via the bus; and
send write data to the bus slave via the bus.
13. The apparatus of claim 12 , wherein the controller circuit is further configured to assert and later release a wait state, via the second signal line, after sending the write address but before sending the write data.
14. An apparatus for operating as a bus slave of a serial bus, the apparatus comprising:
a controller circuit; and
at least one input, output, or input/output port;
wherein the controller circuit is configured to perform a bus operation with a bus master, the bus operation comprising a read operation or a write operation;
wherein, to perform the read operation, the controller circuit is configured to:
receive a first serial clock from the bus master over a first signal line;
receive a read command and a read address from the bus master via a bus comprising at least one bidirectional input/output (I/O) channel, each I/O channel having its own respective signal line, wherein the read command and the read address are substantially edge aligned with one of a rising edge or a falling edge of the first serial clock and substantially center aligned with the other of the rising edge or the falling edge of the first serial clock;
send read data to the bus master via the bus according to the serial clock; and
send a second serial clock to the bus master over a second signal line for use by the bus master as a data strobe, wherein the read data is edge aligned with one of a rising edge or a falling edge of the second serial clock and center aligned with the other of the rising edge or the falling edge of the second serial clock.
15. The apparatus of claim 14 , wherein the bus comprises four bidirectional I/O channels.
16. The apparatus of claim 14 , wherein the controller circuit is further configured to assert and later release a wait state after receiving the read address and before sending the read data, via the second signal line, during which the second serial clock is not sent to the bus master over the second signal line.
17. The apparatus of claim 14 , wherein, to perform the write operation, the controller circuit is configured to:
receive a write command from the bus master via the bus;
receive a write address from the bus master via the bus; and
receive write data from the bus master via the bus.
18. The apparatus of claim 17 , further comprising, after receiving the write address, and before receiving the write data, detecting assertion and later release of a wait state by the bus master, via the second signal line.