3D integrated circuit with enhanced debugging capability
An integrated circuit includes a plurality of layers. A subset of the plurality of layers is reserved for implementing user circuitry. At least a portion of a selected layer of the plurality of layers is reserved for debugging.
1. A method, comprising:
testing a plurality of layers of a 3-dimensional integrated circuit (3D IC), wherein each layer is subdivided into a plurality of regions, wherein the regions from one layer to another are aligned within stacked columns;
determining which regions of the plurality of layers are operational;
determining a number of operational regions in each stacked column; and
for each stacked column including a number of operational regions exceeding a number of operational regions reserved for user circuitry, designating a selected region of a selected layer of the plurality of layers as a debug region.
2. The method of claim 1 , wherein the testing includes testing each region of each of the plurality of layers.
3. The method of claim 1 , further comprising:
for each stacked column of regions including a number of operational regions that equals a number of operational regions reserved for the user circuitry, determining that no region of the stacked column is available as a debug region.
4. The method of claim 1 , further comprising:
disallowing implementation of the user circuitry in any debug region.
5. The method of claim 4 , further comprising:
permitting only debug circuitry to be implemented in any debug region.
6. The method of claim 1 , wherein the 3D IC is one of a plurality of 3D ICs, the method further comprising:
assigning selected ones of the 3D ICs of the plurality of 3D ICs to a group such that, for the selected layer of the plurality of layers, each region of the selected layer is available as a debug region based on a union of debug signatures of the plurality of 3D ICs of the group.
7. The method of claim 6 , further comprising:
generating a histogram specifying available debug regions for 3D ICs of the plurality of 3D ICs not assigned to the group.
8. The method of claim 6 , further comprising:
partitioning a set of probes for the user circuitry into a plurality of subsets, wherein each subset corresponds to a different 3D IC that provides a different debug region.
9. An integrated circuit, comprising:
a plurality of layers, wherein each layer is subdivided into a plurality of regions such that the regions from one layer to another are aligned within stacked columns;
wherein, based on testing of the plurality of layers, a number of regions of each layer of the plurality of layers within each stacked column are designated as operational; and
wherein, for each stacked column including a number of operational regions exceeding a number of operational regions reserved for user circuitry, a selected region of a selected layer of the plurality of layers is designated as a debug region.
10. The integrated circuit of claim 9 , further comprising:
debug circuitry implemented in at least one debug region; and
the user circuitry implemented within one or more non-debug regions of the plurality of layers;
wherein the debug circuitry is operable to probe signals of the user circuitry.
11. The integrated circuit of claim 9 , wherein each layer includes programmable circuitry.
12. The integrated circuit of claim 9 , wherein an entirety of a selected layer of the plurality of layers is reserved for debugging.
13. The integrated circuit of claim 9 , wherein a portion of a selected layer of the plurality of layers is reserved for debugging.
14. The integrated circuit of claim 9 , wherein each stacked column of regions that includes a number of operational regions of different layers that is equal to a number of operational regions reserved for the circuitry lacks a debug region.
15. The integrated circuit of claim 9 , wherein the integrated circuit (IC) is a 3D IC assigned to a group of a plurality of 3D ICs in which a union of debug signatures of the 3D ICs of the group indicate that, for the group, all regions of the selected layer are available for debugging.
16. The integrated circuit of claim 15 , wherein the group of 3D ICs is used to implement a user circuit design in which a set of probes for the user circuitry of the user circuit design is partitioned into a plurality of subsets, and wherein each subset is implemented in a different debug region located in a different one of the plurality of 3D ICs of the group.