IP Library › Granted Patent US 12,575,128
Granted Patent B2
US 12,575,128 · App. 17/810,581 · Granted Mar 10, 2026

Semiconductor structure and method for forming the same

Inventors: Tzu-Ging Lin (Kaohsiung City, TW); Chun-Liang Lai (Hsinchu City, TW); Yun-Chen Wu (Hsinchu, TW); Shun-Hui Yang (Taoyuan County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
H10D30/6215H10D30/0243H10D62/118H10D64/018
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Quick Facts
Patent No.
US 12,575,128
App. No.
17/810,581
Granted
Mar 10, 2026
Kind
B2
Abstract

A semiconductor structure includes a substrate, a multi-gate FET device disposed over the substrate, a first isolation disposed in the substrate, and a second isolation disposed in the substrate. The multi-gate FET device includes a gate structure and epitaxial source/drain structures disposed at two sides of the gate structure. The first isolation includes a first portion and a second portion over the first portion. A top surface of the second portion is aligned with a top surface of the epitaxial source/drain structures. A width of the second portion is different from a width of the first portion.

Claims (48)

1 . A method for forming a semiconductor structure, comprising:

forming a nanosheet stack over a substrate, wherein the nanosheet stack comprises a plurality of nanosheets;

forming a sacrificial gate structure over the nanosheet stack;

forming epitaxial source/drain structures at two sides of the sacrificial gate structure;

removing a portion of the sacrificial gate structure to form a first recess exposing the nanosheet stack after the forming of the epitaxial source/drain structures;

removing portions of the nanosheet stack to form a second recess coupled to the first recess;

forming spacers on sidewalls of the first recess and sidewalls of the second recess after the forming of the epitaxial source/drain structures;

removing a portion of the substrate to form a third recess coupled to the second recess; and

filling the third recess, the second recess and the first recess to form a first isolation.

2 . The method of claim 1 , wherein a bottom of the second recess is higher than bottoms of the epitaxial source/drain structures.

3 . The method of claim 1 , wherein the substrate comprises a second isolation, and a bottom of the third recess is lower than a bottom of the second isolation.

4 . The method of claim 1 , wherein the forming of the third recess comprises an anisotropic etching operation.

5 . The method of claim 1 , further comprising removing the spacers.

6 . The method of claim 1 , further comprising:

removing portions of the nanosheet stack to form the plurality of nanosheets; and

replacing the sacrificial gate structure with a metal gate structure.

7 . A method for forming a semiconductor structure, comprising:

forming a nanosheet stack extending a first direction over a substrate, wherein the nanosheet stack comprises a plurality of nanosheets;

forming a sacrificial gate structure extending a second direction over the nanosheet stack, wherein the second direction is different from the first direction;

forming epitaxial source/drain structures at two sides of the sacrificial gate structure;

forming a first isolation in the sacrificial gate structure, the nanosheet stack and the substrate; and

replacing the sacrificial gate structure with a metal gate structure,

wherein, in the second direction, the first isolation comprises a first portion laterally surrounded by the substrate, a second portion laterally surrounded by the epitaxial source/drain structures, and a third portion surrounded by the metal gate structure,

wherein a bottom of the second portion is in direct contact with the first portion, and a top of the second portion is in direct contact with the third portion,

wherein, in the second direction, a width of the third portion is greater than a width of the first portion.

8 . The method of claim 7 , wherein the substrate comprises a second isolation, and the second isolation is exposed through a sidewall of the third recess.

9 . The method of claim 8 , wherein a bottom of the third recess is lower than a bottom of the second isolation.

10 . The method of claim 7 , further comprising removing the spacers prior to the filling of the third recess, the second recess and the first recess with the insulating material to form the first isolation.

11 . The method of claim 7 , further comprising:

removing portions of the nanosheet stack to form the plurality of nanosheets; and

replacing the sacrificial gate structure with a metal gate structure.

12 . The method of claim 11 , further comprising forming a third isolation in the metal gate structure.

13 . The method of claim 12 , wherein a bottom of the third isolation is higher than a bottom of the first isolation.

14 . The method of claim 12 , further comprising forming a protection layer over the third isolation.

15 . The method of claim 14 , wherein the protection layer and the third isolation comprise a same material.

16 . The method of claim 14 , wherein the protection layer is coupled to the third isolation.

17 . A method for forming a semiconductor structure, comprising:

forming a nanosheet stack extending a first direction over a substrate, wherein the nanosheet stack comprises a plurality of nanosheets;

forming a sacrificial gate structure extending a second direction over the nanosheet stack, wherein the second direction is different from the first direction;

forming epitaxial source/drain structures at two sides of the sacrificial gate structure;

forming a first isolation in the sacrificial gate structure, the nanosheet stack and the substrate; and

replacing the sacrificial gate structure with a metal gate structure,

wherein, in the second direction, the first isolation comprises a first portion laterally surrounded by the substrate, a second portion laterally surrounded by the epitaxial source/drain structures, and a third portion surrounded by the metal gate structure,

wherein a bottom of the second portion is in contact with the first portion, and a top of the second portion is in contact with the third portion,

wherein, in the second direction, a width of the third portion is greater than a width of the first portion.

18 . The method of claim 17 , wherein a width of the second portion is different from the width of the first portion, and different from the width of the third portion.

19 . The method of claim 17 , wherein the substrate comprises a second isolation, and a bottom of the first isolation is lower than a bottom of the second isolation.

20 . The method of claim 19 , wherein the first portion of the first isolation is laterally surrounded by the second isolation in the first direction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 16, 2022
From: LIN, TZU-GING; LAI, CHUN-LIANG; WU, YUN-CHEN; YANG, SHUN-HUI
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Reel/Frame 060822/0842 →
Continuity (1)
Related Publication 20240006535A1 · Jan 4, 2024
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