Electrostatic discharge protection circuit for chip
The present disclosure provides an electrostatic discharge (ESD) protection circuit for a chip, including: a monitoring unit, configured to generate a trigger signal when there is an ESD pulse on a power supply pad; a plurality of controllable drive units, connected to the monitoring unit, and each of the controllable drive units being configured to switch an operating state under a control of a control signal, wherein the operating state includes an output state, and the output state refers to generating a drive signal according to the trigger signal; and a discharge transistor, connected to the plurality of controllable drive units, and configured to be turned on under a drive of the drive signal so as to discharge an electrostatic charge to the ground pad.
1. An electrostatic discharge protection circuit for a chip, wherein the chip comprises a power supply pad and a ground pad, and the electrostatic discharge protection circuit comprises:
a monitoring unit, configured to generate a trigger signal when there is an electrostatic discharge pulse on the power supply pad;
a plurality of controllable drive units, connected to the monitoring unit, and each of the controllable drive units being configured to switch an operating state under a control of a control signal, wherein the operating state comprises an output state, and the output state refers to generating a drive signal according to the trigger signal; and
a discharge transistor, connected to the plurality of controllable drive units, and configured to be turned on under a drive of the drive signal so as to discharge an electrostatic charge to the ground pad; and,
wherein each of the controllable drive units comprises:
a main circuit, configured to generate the drive signal according to the trigger signal when in the output state; and a control circuit, connected to the main circuit, and configured to switch an operating state of the main circuit according to the control signal, wherein the operating state of the main circuit comprises an output state.
2. The electrostatic discharge protection circuit according to claim 1 , wherein
the main circuit is connected between the power supply pad and the ground pad; and
the main circuit is connected to an output terminal of the monitoring unit through the control circuit.
3. The electrostatic discharge protection circuit according to claim 2 , wherein the main circuit comprises:
a first drive transistor, provided with a first terminal connected to the power supply pad; and
a second drive transistor, provided with a first terminal connected to a second terminal of the first drive transistor and a second terminal connected to the ground pad.
4. The electrostatic discharge protection circuit according to claim 3 , wherein the control circuit comprises:
a first switch, provided with a first terminal connected to the output terminal of the monitoring unit and a second terminal connected to a control terminal of the first drive transistor, and configured to be switched from an on state to an off state or from the off state to the on state under the control of the control signal; and
a second switch, provided with a first terminal connected to the output terminal of the monitoring unit and a second terminal connected to a control terminal of the second drive transistor, and configured to be switched from an on state to an off state or from the off state to the on state under the control of the control signal.
5. The electrostatic discharge protection circuit according to claim 4 , wherein the first switch, the second switch, a third switch, a fourth switch, a fifth switch and a sixth switch are one-time programmable memories.
6. The electrostatic discharge protection circuit according to claim 5 , wherein the first switch, the second switch, the third switch, the fourth switch, the fifth switch and the sixth switch are laser fuse devices.
7. The electrostatic discharge protection circuit according to claim 3 , wherein the first drive transistor is a P-type transistor, and the second drive transistor and the discharge transistor are N-type transistors.
8. The electrostatic discharge protection circuit according to claim 1 , wherein the control circuit comprises a first control sub-circuit and a second control sub-circuit;
the main circuit is connected to an output terminal of the monitoring unit; and
the main circuit is connected to the power supply pad through the first control sub-circuit, and the main circuit is connected to the ground pad through the second control sub-circuit.
9. The electrostatic discharge protection circuit according to claim 8 , wherein the main circuit comprises:
a first drive transistor, provided with a control terminal connected to the output terminal of the monitoring unit; and
a second drive transistor, provided with a first terminal connected to a second terminal of the first drive transistor and a control terminal connected to the output terminal of the monitoring unit.
10. The electrostatic discharge protection circuit according to claim 9 , wherein the first control sub-circuit comprises:
a first control transistor, provided with a first terminal connected to the power supply pad and a second terminal connected to a first terminal of the first drive transistor;
a third switch, provided with a first terminal connected to the power supply pad and a second terminal connected to a control terminal of the first control transistor, and configured to be switched from an on state to an off state or from the off state to the on state under the control of the control signal; and
a fourth switch, provided with a first terminal connected to the control terminal of the first control transistor and a second terminal connected to the ground pad, and configured to be switched from an on state to an off state or from the off state to the on state under the control of the control signal.
11. The electrostatic discharge protection circuit according to claim 10 , wherein the second control sub-circuit comprises:
a second control transistor, provided with a first terminal connected to a second terminal of the second drive transistor and a second terminal connected to the ground pad;
a fifth switch, provided with a first terminal connected to the power supply pad and a second terminal connected to a control terminal of the second control transistor, and configured to be switched from an on state to an off state or from the off state to the on state under the control of the control signal; and
a sixth switch, provided with a first terminal connected to the control terminal of the second control transistor and a second terminal connected to the ground pad, and configured to be switched from an on state to an off state or from the off state to the on state under the control of the control signal.
12. The electrostatic discharge protection circuit according to claim 10 , wherein the first control transistor is a P-type transistor, and a second control transistor is an N-type transistor.
13. The electrostatic discharge protection circuit according to claim 12 , wherein a size of the first control transistor is the same as a size of the first drive transistor, and a size of the second control transistor is the same as a size of the second drive transistor.
14. The electrostatic discharge protection circuit according to claim 1 , wherein the monitoring unit comprises:
a monitoring resistor, provided with a first terminal connected to the power supply pad; and
a monitoring capacitor, provided with a first terminal, used as an output terminal of the monitoring unit after connected to a second terminal of the monitoring resistor, and a second terminal connected to the ground pad.