Semiconductor devices with embedded ferroelectric field effect transistors
A device includes a substrate, gate stacks, source/drain (S/D) features over the substrate, S/D contacts over the S/D features, and one or more dielectric layers over the gate stacks and the S/D contacts. A via structure penetrates the one or more dielectric layers and electrically contacts one of the gate stacks and the S/D contacts. And a ferroelectric (FE) stack is over the via structure and directly contacting the via structure, wherein the FE stack includes an FE feature and a top electrode over the FE feature.
1. A device, comprising:
a substrate;
gate stacks and source/drain (S/D) features over the substrate;
S/D contacts over the S/D features;
one or more dielectric layers over the gate stacks and the S/D contacts;
a via penetrating the one or more dielectric layers and electrically contacting one of the gate stacks and the S/D contacts, wherein the via is above the one of the gate stacks and S/D contacts; and
a ferroelectric (FE) stack over the via and directly contacting the via, wherein the FE stack includes an FE feature and a top electrode over the FE feature.
2. The device of claim 1 , wherein the FE feature directly contacts the via.
3. The device of claim 1 , wherein the FE stack further includes a bottom electrode under the FE feature.
4. The device of claim 3 , wherein the bottom electrode directly contacts the via.
5. The device of claim 1 , further comprising a dielectric liner surrounding sidewalls of the FE stack.
6. The device of claim 1 , further comprising a first dielectric layer embedding the FE stack and a conductive feature penetrating the first dielectric layer and directly contacting the top electrode.
7. The device of claim 1 , further comprising a via glue layer between the via and the one or more dielectric layers.
8. A device, comprising:
a substrate;
gate stacks and source/drain (S/D) features over the substrate;
S/D contacts over the S/D features;
gate dielectric caps over the gate stacks;
a gate via penetrating one of the gate dielectric caps and electrically contacting one of the gate stacks, wherein the gate via is above the one of the gate stacks; and
a gate ferroelectric (FE) stack over the gate via and directly contacting the gate via, wherein the gate FE stack includes a FE feature and a top electrode over the FE feature.
9. The device of claim 8 , further comprising:
S/D dielectric caps over the S/D contacts;
an S/D contact via penetrating one of the S/D dielectric caps and electrically contacting one of the S/D contacts, wherein the S/D contact via is above the one of the S/D contacts; and
a S/D FE stack over the S/D contact via and directly contacting the S/D contact via.
10. The device of claim 9 , further comprising one or more dielectric layers over the gate dielectric caps and the S/D dielectric caps, wherein the gate via and the S/D contact via both penetrate the one or more dielectric layers.
11. The device of claim 8 , wherein the FE feature directly contacts the gate via.
12. The device of claim 8 , wherein the gate FE stack further includes a bottom electrode under the FE feature.
13. The device of claim 12 , wherein the bottom electrode directly contacts the gate via.
14. The device of claim 8 , further comprising a dielectric liner surrounding sidewalls of the gate FE stack.
15. The device of claim 8 , further comprising a first dielectric layer embedding the gate FE stack and a conductive feature penetrating the first dielectric layer and directly contacting the top electrode.
16. A device, comprising:
a substrate;
gate stacks and source/drain (S/D) features over the substrate;
S/D contacts over the S/D features;
one or more dielectric layers over the gate stacks and the S/D contacts;
a gate via penetrating the one or more dielectric layers and electrically contacting one of the gate stacks, wherein the gate via is above the one of the gate stacks;
an S/D contact via penetrating the one or more dielectric layers and electrically contacting one of the S/D contacts, wherein the S/D contact via is above the one of the S/D contacts;
a gate ferroelectric (FE) stack over the gate via and directly contacting the gate via; and
an S/D FE stack over the S/D contact via and directly contacting the S/D contact via.
17. The device of claim 16 , wherein each of the gate FE stack and the S/D FE stack includes a FE feature and a top electrode over the FE feature, wherein each of the FE feature directly contacts each of the gate via and the S/D contact via, respectively.
18. The device of claim 16 , wherein each of the gate FE stack and the S/D FE stack further includes a bottom electrode under the FE feature, wherein each of the bottom electrode directly contacts the gate via and the S/D contact via, respectively.
19. The device of claim 17 , further comprising a dielectric liner surrounding sidewalls of each of the gate FE stack and the S/D FE stack.
20. The device of claim 17 , further comprising:
a first dielectric layer embedding each of the gate FE stack and the S/D FE stack; and
a conductive feature penetrating the first dielectric layer and directly contacting the top electrode of each of the gate FE stack and the S/D FE stack.