Methods of forming spacers for semiconductor devices including backside power rails

1. A method comprising:

providing a first transistor structure; and

forming a backside interconnect structure on a backside of the first transistor structure, wherein forming the backside interconnect structure comprises:

forming a first dielectric layer on the backside of the first transistor structure;

removing an epitaxial material adjacent the first dielectric layer to form a first recess;

forming a first via in the first recess and electrically coupled to a first source/drain region of the first transistor structure;

forming a first conductive line on and electrically coupled to the first via;

forming a dielectric spacer adjacent the first conductive line; and

sealing an air spacer adjacent the first conductive line and the dielectric spacer, wherein the first conductive line defines a first boundary of the air spacer, and wherein the dielectric spacer defines a second boundary of the air spacer.

2. The method of claim 1 , further comprising forming a front-side interconnect structure on a front-side of the first transistor structure opposite the backside interconnect structure.

3. The method of claim 1 , wherein sealing the air spacer comprises depositing a second dielectric layer on the first conductive line and the dielectric spacer, wherein the second dielectric layer defines a third boundary of the air spacer.

4. The method of claim 3 , further comprising planarizing the second dielectric layer, the dielectric spacer, and the first conductive line.

5. The method of claim 1 , further comprising:

forming a sacrificial layer adjacent the first conductive line, wherein the dielectric spacer is formed on the sacrificial layer; and

removing the sacrificial layer to form a second recess exposing a side surface of the first conductive line.

6. The method of claim 1 , wherein after sealing the air spacer, the air spacer extends continuously from a side surface of the first conductive line to a side surface of a second conductive line.

7. The method of claim 1 , wherein after sealing the air spacer, an aspect ratio of a height of the air spacer to a width of the air spacer is from 1 to 2.

8. A method comprising:

providing a transistor structure;

forming a front-side interconnect structure on a front-side of the transistor structure; and

forming a backside interconnect structure on a backside of the transistor structure, wherein forming the backside interconnect structure comprises:

forming a backside via on and electrically coupled to a first source/drain region of the transistor structure;

forming a first conductive line on and electrically coupled to the backside via;

forming a first dielectric spacer on a side surface of the first conductive line; and

sealing an air gap adjacent the first dielectric spacer, wherein a side surface of the first dielectric spacer and a side surface of the first conductive line define boundaries of the air gap.

9. The method of claim 8 , wherein forming the backside via comprises:

etching back a semiconductor substrate to expose a first epitaxial material;

removing the first epitaxial material to form a first recess exposing the first source/drain region; and

forming the backside via in the first recess.

10. The method of claim 9 , further comprising replacing the semiconductor substrate with a first dielectric layer.

11. The method of claim 8 , wherein forming the backside interconnect structure further comprises:

depositing a first dielectric layer on the backside of the transistor structure and on the backside via;

etching the first dielectric layer to form a first recess exposing the backside via; and

forming the first conductive line in the first recess.

12. The method of claim 11 , further comprising:

etching back the first dielectric layer;

forming the first dielectric spacer on the first dielectric layer; and

removing the first dielectric layer.

13. The method of claim 8 , wherein sealing the air gap comprises depositing a first dielectric layer on the first conductive line and the first dielectric spacer, wherein a surface of the first dielectric layer proximal the transistor structure defines a boundary of the air gap.

14. The method of claim 13 , further comprising planarizing the first dielectric layer, the first dielectric spacer, and the first conductive line.

15. A method comprising:

providing a first transistor on a first substrate;

thinning a backside of the first substrate;

removing a first epitaxial material to form a first recess on the backside of the first substrate;

forming a first backside via in the first recess;

forming a first dielectric layer on the first backside via;

forming a first conductive line on the first backside via in the first dielectric layer;

thinning the first dielectric layer;

forming a first spacer on the first dielectric layer adjacent the first conductive line;

removing the first dielectric layer; and

sealing an air spacer adjacent the first spacer and the first conductive line.

16. The method of claim 15 , wherein removing the first epitaxial material exposes a first source/drain region of the first transistor.

17. The method of claim 15 , wherein sealing the air spacer comprises forming a second dielectric layer on the first spacer.

18. The method of claim 17 , wherein the second dielectric layer, the first spacer, and the first conductive line define boundaries of the air spacer.

19. The method of claim 15 , further comprising forming a second conductive line on a second backside via in the first dielectric layer, wherein the first conductive line is electrically coupled to a first source/drain region of the first transistor, and wherein the second conductive line is electrically coupled to a second source/drain region of the first transistor, wherein the first dielectric layer extends from the first conductive line to the second conductive line.

20. The method of claim 19 , wherein removing the first dielectric layer exposes side surfaces of the first conductive line and the second conductive line.