IP Library Granted Patent US 12,543,579
Granted Patent B2
US 12,543,579 · App. 17/813,380 · Granted Feb 3, 2026

Dual side cooled power module with three-dimensional direct bonded metal substrates

Inventors: Yong Liu (Cumberland Foreside, ME); Yusheng Lin (Phoenix, AZ); Jerome Teysseyre (Scottsdale, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/49838H01L23/367H01L24/29H01L24/30H01L24/32H01L24/33H01L23/3735H01L25/072H01L25/18H01L2224/29111H01L2224/2912H01L2224/29139H01L2224/29147H01L2224/30505H01L2224/32227H01L2224/32238H01L2224/33181H01L2924/0132H01L2924/0133H01L2924/15153H01L2924/15159H01L2924/1517
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Quick Facts
Patent No.
US 12,543,579
App. No.
17/813,380
Granted
Feb 3, 2026
Kind
B2
Abstract

A substrate includes a ceramic tile and a three-dimensional (3D) conductive structure. The 3D conductive structure includes a planar base layer having a bottom surface bonded to a top surface of the ceramic tile, and a block disposed above the planar base layer. The block is monolithically integrated with the planar base layer. A top surface of the block is configured as a die attach pad. The planar base layer has a base vertical thickness from the top surface of the ceramic tile to a top surface of the planar base layer. The block and the planar base layer have a combined vertical thickness from the top surface of the ceramic tile to a top surface of the block that is greater than the base vertical thickness.

Claims (46)

1 . A substrate comprising:

a ceramic tile; and

a three-dimensional conductive structure including:

a planar base layer having a bottom surface bonded to a top surface of the ceramic tile, the planar base layer having a base vertical thickness from the top surface of the ceramic tile to a top surface of the planar base layer,

a block disposed above the planar base layer and integrated with the planar base layer without an intervening joint, the block and the planar base layer having a first combined vertical thickness from the top surface of the ceramic tile to a top surface of the block, the first combined vertical thickness being greater than the base vertical thickness, the top surface of the block being configured as a die attach pad; and

a pillar disposed above the planar base layer and integrated with the planar base layer without an intervening joint, the pillar and the planar base layer having a second combined vertical thickness from the top surface of the ceramic tile to a top surface of the pillar, the second combined vertical thickness being greater than the first combined vertical thickness.

2 . The substrate of claim 1 , wherein the block is a first block, the die attach pad being a first die attach pad, and

the three-dimensional conductive structure including:

a second block disposed above the planar base layer and integrated with the planar base layer without an intervening joint, the second block being separated from the first block by a gap, the second block and the planar base layer having the first combined vertical thickness, a top surface of the second block being configured as a second die attach pad.

3 . The substrate of claim 1 , wherein the block is a first block and the die attach pad is a first die attach pad, the combined vertical thickness being a first combined vertical thickness, and wherein the three-dimensional conductive structure includes:

a second block disposed above the planar base layer and integrated with the planar base layer without an intervening joint, the second block being separated from the first block by a gap, the second block and the planar base layer having a third combined vertical thickness different than the first combined vertical thickness, the top surface of the second block being configured as a second die attach pad.

4 . The substrate of claim 1 , wherein a portion of the top surface of block configured as a die attach pad includes a recessed cavity configured to hold a semiconductor die in position on the block.

5 . The substrate of claim 1 , wherein the vertical base thickness between the top surface of the ceramic tile and the top surface of the planar base layer is less than 0.4 mm.

6 . The substrate of claim 1 , wherein the first combined vertical thickness from the top surface of the ceramic tile to the top surface of the block is at least 0.6 mm.

7 . The substrate of claim 1 , wherein the block has a length and a width in a lateral plane, the length and the width each being greater than 0.2 mm long.

8 . The substrate of claim 1 , wherein the three-dimensional conductive structure is a metal or metal alloy structure bonded to the ceramic tile.

9 . The substrate of claim 1 , wherein the block is a first block that is separated from the pillar by a first gap, the three-dimensional conductive structure including:

a second block disposed above the planar base layer and integrated with the planar base layer without any intervening joint, the second block being separated from the pillar by a second gap, the first gap and second gap being on opposite sides of the pillar, the second block and the planar base layer having the first combined vertical thickness, a top surface of the second block being configured as a second die attach pad.

10 . A substrate comprising:

a ceramic tile; and

a three-dimensional conductive structure including:

a planar base layer having a bottom surface bonded to a top surface of the ceramic tile, the planar base layer having a vertical base thickness between the top surface of the ceramic tile and a top surface of the planar base layer,

a block disposed above the planar base layer and integrated with the planar base layer without an intervening joint, the block having a vertical block thickness from the top surface of the planar base layer to a top surface of the block, the top surface of the block being configured as a die attach pad,

a pillar disposed above the planar base layer and integrated with the planar base layer without an intervening joint, the pillar having a vertical pillar thickness from the top surface of the planar base layer to a top surface of the pillar, the vertical pillar thickness being greater than the vertical block thickness.

11 . The substrate of claim 10 , wherein the block is a first block and the die attach pad is a first die attach pad,

the three-dimensional conductive structure including:

a second block disposed above the planar base layer and integrated with the planar base layer without any intervening joint, the second block being separated from the first block by a gap, the second block and the planar base layer having a combined vertical thickness, the top surface of the second block being configured as a second die attach pad.

12 . The substrate of claim 10 , wherein the block is a first block, the die attach pad is a first die attach pad, and the vertical block thickness is a first vertical block thickness,

the three-dimensional conductive structure including:

a second block disposed above the planar base layer and integrated with the planar base layer without any intervening joint, the second block being separated from the first block by a gap, the second block and the planar base layer having a second vertical block thickness different than the first vertical block thickness, the top surface of the second block being configured as a second die attach pad.

13 . The substrate of claim 10 , wherein a portion of the top surface of block configured as a die attach pad includes a recessed cavity configured to hold a semiconductor die in position on the block.

14 . A package comprising:

a first direct bonded metal (DBM) substrate including:

a planar base layer having a bottom surface bonded to a top surface of a ceramic tile, the planar base layer having a vertical base thickness from the top surface of the ceramic tile to a top surface of the planar base layer,

a block disposed above the planar base layer and integrated with the planar base layer without any intervening joint, the block having a vertical block thickness from the top surface of the planar base layer to a top surface of the block, the top surface of the block being configured as a die attach pad, and

a pillar disposed above the planar base layer and integrated with the planar base layer without an intervening joint, the pillar having a vertical pillar thickness from the top surface of the planar base layer to a top surface of the pillar, the vertical pillar thickness being greater than the vertical block thickness;

a semiconductor die disposed on the die attach pad; and

a second DBM substrate disposed on a top of the semiconductor die.

15 . The package of claim 14 , wherein a portion of the top surface of block configured as the die attach pad includes a recessed cavity configured to hold a semiconductor die in position on the block.

16 . The package of claim 14 , wherein a first solder layer bonds the semiconductor die to the die attach pad.

17 . The package of claim 16 , wherein the first solder layer is a lead-free tin-antimony alloy.

18 . The package of claim 14 , wherein a second solder layer bonds the second substrate to the semiconductor die.

19 . The package of claim 18 , wherein the second solder layer is a lead-free tin-silver-copper alloy.

20 . The package of claim 14 , wherein a top surface of the pillar is bonded to the second DBM substrate disposed on the top of the semiconductor die.

21 . The package of claim 14 , wherein the block is a first block that is separated from the pillar by a first gap, the first DBM substrate including:

a second block disposed above the planar base layer and integrated with the planar base layer without any intervening joint, the second block being separated from the pillar by a second gap, the first gap and second gap being on opposite sides of the pillar, the second block and the planar base layer having the first combined vertical thickness, a top surface of the second block being configured as a second die attach pad.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 061879, FRAME 0655 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: FAIRCHILD SEMICONDUCTOR CORPORATION; SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 064123/0001 →
SECURITY INTEREST Recorded Nov 3, 2022
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 061879/0655 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2022
From: LIU, YONG; LIN, YUSHENG; TEYSSEYRE, JEROME
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 060547/0917 →