Circuit structure and related method to compensate for sense amplifier leakage
Embodiments of the disclosure provide a circuit structure and related method to compensate for sense amplifier leakage. A circuit structure according to the disclosure includes a reference voltage generator coupling a supply voltage and a reference line to a sense amplifier. A multiplexer within the reference voltage generator is coupled to the reference line. The multiplexer includes a plurality of transistors each having a gate terminal coupled to ground.
1. A circuit structure comprising:
a reference voltage generator coupling a supply voltage and a reference line to a sense amplifier having a plurality of phases; and
a multiplexer within the reference voltage generator and coupled to the reference line, the multiplexer including a plurality of transistors each configured to mirror a current leakage within a respective phase of the sense amplifier and having a gate terminal coupled to ground,
wherein each respective phase of the sense amplifier differs from at least one other phase of the sense amplifier.
2. The circuit structure of claim 1 , wherein the sense amplifier is one of a plurality of sense amplifiers coupled to the reference voltage generator, each of the plurality of sense amplifiers having a column multiplexer with the plurality of phases, wherein the plurality of phases within each column multiplexer has a same current leakage.
3. The circuit structure of claim 1 , wherein the plurality of transistors includes:
a first transistor configured to mirror a current leakage in a two-to-one phase, of the plurality of phases of the sense amplifier;
a second transistor configured to mirror a current leakage in a four-to-one phase, of the plurality of phases of the sense amplifier; and
a third transistor configured to mirror a current leakage in an eight-to-one phase, of the plurality of phases of the sense amplifier.
4. The circuit structure of claim 1 , wherein the multiplexer is configured to reduce a reference current from the reference line by an amount approximately equal to the-current leakage in the sense amplifier.
5. The circuit structure of claim 1 , wherein the sense amplifier is configured to compare a current from a selected bit cell with an output from the reference voltage generator to output a current indicating a logic level in the selected bit cell.
6. A circuit structure comprising:
a reference voltage generator coupled to a supply voltage and a reference line to a plurality of sense amplifiers each having an amplifier multiplexer with a plurality of phases;
a multiplexer within the reference voltage generator and coupled to the reference line, the multiplexer including a plurality of transistors each configured to mirror a current leakage within a respective phase of a respective sense amplifier of the plurality of sense amplifiers and having a gate terminal coupled to ground, wherein the reference voltage generator outputs a reference voltage based on a reference current in the reference line, the supply voltage, and the current leakage and
wherein each respective phase of the sense amplifier, of the plurality of sense amplifiers, differs from at least one other phase of the sense amplifier.
7. The circuit structure of claim 6 , wherein each amplifier multiplexer is of substantially uniform size.
8. The circuit structure of claim 6 , wherein the multiplexer and each amplifier multiplexer are of substantially uniform size.
9. The circuit structure of claim 6 , wherein the plurality of transistors of the multiplexer includes:
a first transistor configured to mirror a current leakage in a two-to-one phase, of the plurality of phases of the amplifier multiplexer of one of the plurality of sense amplifiers;
a second transistor configured to mirror a current leakage in a four-to-one phase, of the plurality of phases of the amplifier multiplexer of one of the plurality of sense amplifiers; and
a third transistor configured to mirror a current leakage in an eight-to-one phase, of the plurality of phases of the amplifier multiplexer of one of the plurality of sense amplifiers.
10. The circuit structure of claim 6 , wherein the multiplexer within the reference voltage generator is configured to reduce the reference current by an amount approximately equal to a current leakage in each of the plurality of sense amplifiers.
11. A method for generating a reference voltage for at least one sense amplifier of a plurality of sense amplifiers, each sense amplifier having an amplifier multiplexer with a plurality of phases, the method comprising:
transmitting a supply voltage and a reference current to a reference voltage generator to output the reference voltage, wherein the reference voltage generator includes a multiplexer coupled to a reference line, the multiplexer including a plurality of transistors each configured to mirror a current leakage within a respective phase of the sense amplifier and having a gate terminal coupled to ground; and
transmitting the reference voltage to the plurality of sense amplifiers,
wherein each respective phase of the sense amplifier, of the plurality of sense amplifiers, differs from at least one other phase of the sense amplifier.
12. The method of claim 11 , wherein the multiplexer mirrors the current leakage current through:
a first transistor, of the plurality of transistors, configured to mirror a current leakage in a two-to-one phase, of the plurality of phases of the sense amplifier;
a second transistor, of the plurality of transistors, configured to mirror a current leakage in a four-to-one phase, of the plurality of phases of the sense amplifier; and
a third transistor, of the plurality of transistors, configured to mirror a current leakage in an eight-to-one phase, of the plurality of phases of the sense amplifier.
13. The method of claim 11 , wherein transmitting the supply voltage and the reference current to the reference voltage generator causes the multiplexer of the reference voltage generator to reduce the reference current by an amount approximately equal to a current leakage in the sense amplifier.
14. The method of claim 11 , further comprising comparing, via the sense amplifier, a voltage in a selected bit cell with the reference voltage to output a voltage indicating a logic level in the selected bit cell.