Leakage compensation read method for memory device
A memory device including an array of memory cells including bit lines, and biasing circuitry cells. A sense amplifier has a data line input connected to a data line, and a reference input. The controllable reference current source can be connected to the reference input of the sense amplifier. Control circuits on the device are configured to cause execution of a read operation, where the read operation includes a first phase in which the array is biased to induce leakage current on the selected bit line, and a second phase in which the array is biased to read a selected memory cell on the selected bit line. A circuit on the device is configured to sample the leakage current in the first phase, and to control the controllable reference current source during the second phase, as a function of the sampled leakage current.
1. A memory device, comprising:
an array of memory cells including bit lines, and biasing circuitry to apply bias arrangements to the array of memory cells;
a sense amplifier having a data line input connected to a data line, and a reference input;
a column decoder coupled to bit lines in the array to connect a selected bit line to the data line;
a data line load circuit connected to the data line;
a controllable reference current source connected to the reference input, and having a control input;
control circuits to cause execution of a read operation, including a first phase in which the array is biased to induce leakage current on the selected bit line and a second phase in which the array is biased to read a selected memory cell on the selected bit line; and
a circuit to sample the leakage current in the first phase, and provide a control signal to the control input of the controllable reference current source during the second phase as a function of the sampled leakage current;
wherein the circuit to sample the leakage current comprises a current mirror circuit coupled to the data line load circuit which generates a sample current, and a capacitor connected to be charged by the sample current during the first phase, and connected to provide the control signal during the second phase.
2. The device of claim 1 , wherein the controllable reference current source includes a reference current load circuit, and the control circuits disable the reference current load circuit during the first phase.
3. The device of claim 1 , wherein the data line load circuit includes a first branch enabled during the first phase and a second branch enabled during the second phase; and
the circuit to sample the leakage current is connected to the second branch.
4. The device of claim 3 , wherein:
the current mirror circuit is coupled to the first branch of the data line load circuit;
and including
a switch to connect the capacitor to the sample current during the first phase, and to connect the capacitor to provide the control signal during the second phase.
5. A method for sensing data in a memory array, comprising:
selecting a memory cell coupled to a selected bit line;
biasing the memory array to induce leakage current through the memory cells on the selected bit line;
sampling the leakage current;
biasing the memory array to induce read current through the selected memory cell on the selected bit line;
generating a leakage compensation current isolated from the read current in response to the sampled leakage current; and
sensing the data based on the read current and the compensation current; wherein sampling the leakage current includes enabling a current mirror circuit to generate a sample current as a function of the leakage current on the selected bit line, and generating a measure of the sample current.
6. The method of claim 5 , including generating a measure of the sample current by applying the sample current to charge a capacitor to a sample voltage.
7. The method of claim 5 , including sampling and holding a voltage generated using a function of the leakage current, and applying the voltage to a controllable current source to generate the compensation current.
8. A memory device, comprising:
an array of memory cells including bit lines, and biasing circuitry to apply bias arrangements to the array of memory cells;
a sense amplifier having a data line input connected to a data line, and a reference input;
a column decoder coupled to bit lines in the array to connect a selected bit line to the data line;
a data line load circuit connected to the data line;
a reference current source connected to the reference input;
a controllable compensation circuit coupled to the sense amplifier, and having a control input;
control circuits to cause execution of a read operation, including a leakage sampling phase in which the array is biased to induce leakage current on the selected bit line and a sensing phase in which the array is biased to read a selected memory cell on the selected bit line; and
a current mirror circuit coupled to the data line load circuit which generates a sample current, and a capacitor connected to be charged by the sample current during the leakage sampling phase, and connected to the control input of a controllable compensation current source during the sensing phase.
9. The device of claim 8 , wherein the controllable compensation circuit is connected to the reference current source.
10. The device of claim 8 , wherein the reference current source includes a reference current load circuit, and the control circuits disable the reference current load circuit during the leakage sampling phase.
11. The device of claim 8 , wherein the data line load circuit includes a first branch enabled during the leakage sampling phase and a second branch enabled during the sensing phase; and the current mirror circuit is coupled to the first branch of the data line load circuit; and including:
a switch to connect the capacitor to the sample current during the leakage sampling phase, and to connect the capacitor to provide a control signal during the sensing phase.