Memory structure and manufacturing method thereof, and semiconductor structure

1 . A semiconductor structure, comprising:

a columnar epitaxial structure, extending in a first direction;

a grounding structure, wrapping one end of the columnar epitaxial structure;

a bit line structure, wrapping the other end of the columnar epitaxial structure;

a columnar capacitor structure, surrounding the columnar epitaxial structure and located between the grounding structure and the bit line structure; and

a word line structure, surrounding the columnar epitaxial structure and located between the bit line structure and the columnar capacitor structure;

a capacitor isolation structure, surrounding the columnar epitaxial structure and located between the grounding structure and the columnar capacitor structure,

wherein a part of the columnar epitaxial structure is wrapped by the capacitor isolation structure, and a cross-sectional area of an end of the columnar epitaxial structure close to the grounding structure is less than a cross-sectional area of an end of the columnar epitaxial structure distant from the grounding structure.

2 . The semiconductor structure according to claim 1 , wherein a cross-sectional area of a part of the columnar epitaxial structure wrapped by the grounding structure is less than a cross-sectional area of a part of the columnar epitaxial structure wrapped by the columnar capacitor structure; and

the grounding structure comprises a conductive contact layer and a grounding pad sequentially stacked from inside to outside;

wherein, the conductive contact layer wraps an end of the columnar epitaxial structure distant from the bit line structure.

3 . The semiconductor structure according to claim 2 , wherein a sum of lengths of parts of the columnar epitaxial structure wrapped by the grounding structure and the capacitor isolation structure is [10 nm, 100 nm].

4 . The semiconductor structure according to claim 2 , wherein a cross section of the part of the columnar epitaxial structure wrapped by the grounding structure is square, with an edge length of [1 nm, 20 nm].

5 . The semiconductor structure according to claim 2 , wherein the conductive contact layer is made of a metal conductive material; and

the grounding pad is made of a metal conductive material and/or a non-metal conductive material.

6 . The semiconductor structure according to claim 1 , wherein the word line structure comprises a gate oxide layer and a gate metal layer sequentially stacked from inside to outside;

the gate oxide layer surrounds the columnar epitaxial structure; the gate metal layer surrounds the gate oxide layer; and

a cross section of a part of the columnar epitaxial structure surrounded by the gate oxide layer is square, with an edge length of [30 nm, 100 nm].

7 . The semiconductor structure according to claim 6 , wherein an outer boundary of a cross section of the gate oxide layer is square, and the gate oxide layer has a thickness of [4.5 nm, 8 nm].

8 . The semiconductor structure according to claim 6 , wherein an outer boundary of a cross section of the gate metal layer is square, and the gate metal layer has a thickness of [4 nm, 10 nm].

9 . The semiconductor structure according to claim 6 , wherein the columnar epitaxial structure comprises:

a conductive pillar, extending in the first direction and doped with a first type;

a source-region conductive layer, wrapping one end of the conductive pillar, located between the bit line structure and the conductive pillar, and doped with a second type;

a channel-region conductive layer, surrounding the conductive pillar, located between the gate oxide layer and the conductive pillar, and doped with the first type; and

a drain-region conductive layer, surrounding the conductive pillar, located between the columnar capacitor structure and the conductive pillar, and doped with the second type.

10 . A memory structure, comprising: a substrate; and a plurality of target body structures formed on the substrate, extending in a second direction, and arranged at intervals in a third direction;

wherein, each of the plurality of target body structures comprises a plurality of semiconductor structures arranged at intervals in the second direction, and the semiconductor structures are the semiconductor structure according to claim 1 ; word line structures in adjacent two of the semiconductor structures in the second direction insulate from each other; and bit line structures in adjacent two of the target body structures in the third direction insulate from each other; and

every two of the first direction, the second direction, and the third direction are perpendicular to each other.

11 . A method of manufacturing a memory structure, comprising:

providing a substrate; and

forming a plurality of target body structures, extending in a second direction and arranged at intervals in a third direction, on the substrate;

wherein, each of the plurality of target body structures comprises a plurality of semiconductor structures arranged at intervals in the second direction, and the semiconductor structures are the semiconductor structure according to claim 1 ; word line structures in adjacent two of the semiconductor structures in the second direction insulate from each other; and bit line structures in adjacent two of the target body structures in the third direction insulate from each other; and

every two of the first direction, the second direction, and the third direction are perpendicular to each other.

12 . The method according to claim 11 , wherein the forming a plurality of target body structures, extending in a second direction and arranged at intervals in a third direction, on the substrate comprises:

etching an end of the columnar epitaxial structure distant from the bit line structure in the first direction, and forming an interconnection structure, a cross-sectional area of the interconnection structure being less than a cross-sectional area of a part of the columnar epitaxial structure wrapped by the columnar capacitor structure, and a cross section being perpendicular to the first direction; and

siliconizing an end of the interconnection structure distant from the bit line structure in the first direction, and forming a conductive contact layer.

13 . The method according to claim 12 , after the conductive contact layer is formed, the method further comprises:

forming a capacitor isolation structure, the capacitor isolation structure surrounding the columnar epitaxial structure and being located between the conductive contact layer and the columnar capacitor structure; and

forming a grounding pad, the grounding pad wrapping the conductive contact layer; wherein, the conductive contact layer and the grounding pad constitute the grounding structure; and

two adjacent ones of the grounding structures in the second direction are electrically connected to each other; and two adjacent ones of the grounding structures in the third direction insulate from each other to form the target body structure.

14 . The method according to claim 11 , wherein the forming a plurality of target body structures, extending in a second direction and arranged at intervals in a third direction, on the substrate further comprises:

sequentially forming a gate oxide layer and a gate metal layer, sequentially stacked from inside to outside, on the columnar epitaxial structure, the gate oxide layer surrounding the columnar epitaxial structure, and the gate metal layer surrounding the gate oxide layer;

wherein, a cross section of a part of the columnar epitaxial structure surrounded by the gate oxide layer is square, with an edge length of [30 nm, 100 nm], and the cross section is perpendicular to the first direction; and/or,

an outer boundary of a cross section of the gate oxide layer is square, and the gate oxide layer has a thickness of [4.5 nm, 8 nm]; and/or,

an outer boundary of a cross section of the gate metal layer is square, and the gate metal layer has a thickness of [4 nm, 10 nm].