IP Library Granted Patent US 12,622,312
Granted Patent B2
US 12,622,312 · App. 17/816,450 · Granted May 5, 2026

Multichip module supports and related methods

Inventors: Francis J. Carney (Mesa, AZ); Michael J. Seddon (Gilbert, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/31H01L23/528H01L23/562H01L23/60
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Quick Facts
Patent No.
US 12,622,312
App. No.
17/816,450
Granted
May 5, 2026
Kind
B2
Abstract

Implementations of a semiconductor device may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be formed by at least two semiconductor die. The warpage of one of the first largest planar surface or the second largest planar surface may be less than 200 microns.

Claims (30)

1 . A method of forming a semiconductor device package comprising:

permanently coupling a material to a first semiconductor die and to a second semiconductor die at a largest planar surface, a thickness, or any combination thereof of each of the first semiconductor die and the second semiconductor die; and

reducing a warpage of the largest planar surface of the first semiconductor die and a warpage of the largest planar surface of the second semiconductor die comprised in the semiconductor device package to less than 200 microns through the material;

wherein the largest planar surface of the first semiconductor die and the largest planar surface of the second semiconductor die lie in a same plane.

2 . The method of claim 1 , wherein the material comprises two or more layers.

3 . The method of claim 1 , wherein the thickness is between 0.1 microns and 125 microns.

4 . The method of claim 1 , wherein permanently coupling the material to the first semiconductor die and to the second semiconductor die occurs after the first semiconductor die and the second semiconductor die have been singulated from a substrate comprising a plurality of semiconductor die.

5 . The method of claim 1 , wherein the material comprises a mold compound.

6 . The method of claim 1 , wherein a perimeter of the first semiconductor die comprises a closed shape and a perimeter of the second semiconductor die comprises a closed shape.

7 . The method of claim 1 , further comprising permanently coupling a second material to the first semiconductor die and to the second semiconductor die at the largest planar surface, the thickness, or any combination thereof of each of the first semiconductor die and the second semiconductor die.

8 . The method of claim 7 , wherein the material and the second material comprise permanent die support structures.

9 . A method of forming a semiconductor device package comprising:

temporarily coupling a material to a first semiconductor die and to a second semiconductor die at a largest planar surface, a thickness, or any combination thereof of each of the first semiconductor die and the second semiconductor die;

reducing a warpage of the largest planar surface of the first semiconductor die and a warpage of the largest planar surface of the second semiconductor die comprised in the semiconductor device package to less than 200 microns through the material; and

removing the material from the first semiconductor die and the second semiconductor die;

wherein the largest planar surface of the first semiconductor die and the largest planar surface of the second semiconductor die lie in a same plane.

10 . The method of claim 9 , further comprising removing the material using one of light, etching, peeling, ultrasonic energy, grinding, or any combination thereof.

11 . The method of claim 9 , further comprising removing the material after bonding the first semiconductor die and the second semiconductor die to one of a substrate, a leadframe, an additional die, a lead, a redistribution layer, or any combination thereof.

12 . The method of claim 9 , wherein the material comprises two or more layers.

13 . The method of claim 9 , wherein the thickness is between 0.1 microns and 125 microns.

14 . The method of claim 9 , wherein temporarily coupling the material to the first semiconductor die and to the second semiconductor die occurs after the first semiconductor die and the second semiconductor die have been singulated from a substrate comprising a plurality of semiconductor die.

15 . A method of reinforcing a semiconductor device comprising:

one of permanently coupling or temporarily coupling a material to a first semiconductor die and to a second semiconductor die coupled together in a single semiconductor device at one of a largest planar surface, a thickness, or any combination of each of the first semiconductor die and the second semiconductor die; and

reducing a warpage of the largest planar surface of the first semiconductor die and the largest planar surface of the second semiconductor die to less than 200 microns through the material;

wherein the largest planar surface of the first semiconductor die and the largest planar surface the second semiconductor die lie in a same plane when coupled together by the material.

16 . The method of claim 15 , wherein the thickness of the first semiconductor die and the thickness of the second semiconductor die are each between 0.1 microns and 125 microns.

17 . The method of claim 15 , wherein the material is a mold compound.

18 . The method of claim 15 , further comprising removing the material from the first semiconductor die and from the second semiconductor die using one of light, etching, peeling, ultrasonic energy, grinding, or any combination thereof.

19 . The method of claim 15 , wherein the material comprises two or more layers.

20 . The method of claim 15 , further comprising removing the material after bonding the first semiconductor die and the second semiconductor die to one of a substrate, a leadframe, an additional die, a lead, a redistribution layer, or any combination thereof.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 061879, FRAME 0655 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: FAIRCHILD SEMICONDUCTOR CORPORATION; SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 064123/0001 →
SECURITY INTEREST Recorded Nov 3, 2022
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 061879/0655 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2022
From: CARNEY, FRANCIS J.; SEDDON, MICHAEL J.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 060682/0115 →