Self clocked low power doubling charge pump

1. A charge pump circuit comprising:

a charge pump with a low voltage terminal, a high voltage terminal, and a clock input;

a voltage divider circuit with a first input coupled to the low voltage terminal, a second input coupled to the high voltage terminal, and an output configured to provide a divided voltage;

a comparator with a first input configured to receive the divided voltage, a second input coupled to the low voltage terminal, a reset input, and a comparator output;

a pulse generator with an input coupled to the comparator output and an output coupled to the reset input and the clock input; and

a multiplexer configured to selectively couple the output of the pulse generator to the clock input during a sleep mode based on a sleep mode signal, and to selectively couple a clock signal to the clock input during a wake mode based on the sleep mode signal.

2. The charge pump circuit of claim 1 , wherein the voltage divider circuit further comprises:

a reference current generator with an input coupled to the low voltage terminal, and a reference current generator output;

a current mirror with a current mirror input coupled to the reference current generator output, and a current mirror output; and

a voltage divider with a first terminal coupled to the high voltage terminal, a second terminal coupled to the current mirror output, and an output providing the divided voltage.

3. The charge pump circuit of claim 2 , wherein the voltage divider further comprises:

a first n-type metal oxide semiconductor (NMOS) transistor with a source coupled to the current mirror output, a drain, and a gate;

a second NMOS transistor with a source coupled to the drain of the first NMOS transistor, a drain, and a gate coupled to the drain of the second NMOS transistor and to the gate of the first NMOS transistor;

a first PMOS transistor with a drain coupled to the source of the second NMOS transistor, a source, and a gate coupled to the drain of the first PMOS transistor; and

a second PMOS transistor with a source coupled to the high voltage terminal, a drain coupled to the source of the first PMOS transistor, and a gate coupled to the gate of the first PMOS transistor.

4. The charge pump circuit of claim 3 , wherein:

the second PMOS transistor has an adjustable voltage threshold (Vth) under control of a first control input; and

the first NMOS transistor has an adjustable Vth under control of a second control input.

5. The charge pump circuit of claim 2 , wherein the reference current generator comprises:

a third NMOS transistor with a source coupled to the current mirror input, a drain, and a gate coupled to the drain of the third NMOS transistor;

a third PMOS transistor with a drain coupled to the source of the first NMOS transistor, a source coupled to the drain of the third NMOS transistor, and a gate coupled to the drain of the third PMOS transistor; and

a fourth PMOS transistor with a source coupled to the low voltage terminal, a drain coupled to the source of the third PMOS transistor, and a gate coupled to the gate of the first PMOS transistor.

6. The charge pump circuit of claim 5 , wherein the current mirror further comprises:

a fourth NMOS transistor with a source coupled to ground, a drain coupled to the current mirror input, and a gate coupled to the gate of the third NMOS transistor; and

a fifth NMOS transistor with a source coupled to ground, a drain coupled to the current mirror output, and a gate coupled to the gate of the fourth NMOS transistor.

7. The charge pump circuit of claim 1 , wherein the charge pump comprises:

a first NMOS transistor with a source coupled to a negative supply rail, a drain, and a gate coupled to the clock input;

a first PMOS transistor with a source coupled to the low voltage terminal, a gate coupled to the clock input, and a drain coupled to the drain of the first NMOS transistor;

a second NMOS transistor with a source coupled to the low voltage terminal, a drain, and a gate;

a second PMOS transistor with a source coupled to the high voltage terminal, a drain coupled to the drain of the second NMOS transistor, and a gate;

an output capacitor with a first terminal coupled to the drain of the first PMOS transistor and a second terminal coupled to the drain of the second PMOS transistor;

a drive capacitor with a first terminal coupled to the clock input and a second terminal coupled to the gates of the second NMOS transistor and the second PMOS transistor;

a third NMOS transistor with a source coupled to the low voltage terminal, a gate coupled to the second terminal of the output capacitor, and a drain coupled to the second terminal of the drive capacitor; and

a third PMOS transistor with a source coupled to the high voltage terminal, a gate coupled to the second terminal of the output capacitor, and a drain coupled to the drain of the third NMOS transistor.

8. The charge pump circuit of claim 7 , wherein:

the first and second NMOS transistors of the charge pump and the first and second PMOS transistors of the charge pump are power MOSFETs; and

the output capacitor is an external capacitor.

9. The charge pump circuit of claim 1 , wherein the charge pump is driven without using an oscillator or clock signal during the sleep mode.

10. A method of providing a high voltage from a low supply voltage during a sleep mode and a wake mode on an integrated circuit, the method comprising:

based on a sleep mode signal, selectively coupling a pulse generator's output signal to a charge pump's clock input during the sleep mode, wherein the charge pump is driven without using a clock signal during the sleep mode;

driving the pulse generator based on a comparison of the low supply voltage and the high voltage;

resetting the comparison based on the pulse generator's output signal; and

based on the sleep mode signal, selectively coupling a clock signal to the clock input during the wake mode.

11. The method of claim 10 , wherein the comparison comprises a comparison of the low supply voltage and a predetermined portion of the high voltage, and wherein the method further comprises:

creating the predetermined portion of the high voltage with a voltage divider circuit comprising:

a reference current generator with an input supplied with the low supply voltage and a reference current generator output;

a current mirror with a current mirror input coupled to the reference current generator output, and a current mirror output; and

a voltage divider with a first terminal receiving the high voltage, a second terminal coupled to the current mirror output, and an output providing the predetermined portion of the high voltage.

12. The method of claim 11 , further comprising:

adjusting the predetermined portion of the high voltage to a second predetermined portion of the high voltage by adjusting two transistors in the voltage divider.

13. The method of claim 10 , further comprising:

configuring the charge pump to operate in one of a boost mode and a buck mode; and

operating in the configured mode without an oscillator driving the charge pump.

14. The method of claim 10 , wherein the charge pump is driven without using an oscillator during the sleep mode.

15. The method of claim 10 ,

wherein the pulse generator's output signal pulses at irregular intervals, and wherein

the comparison comprises a comparison of the low supply voltage and a predetermined portion of the high voltage.

16. An integrated circuit comprising:

charge pump circuit comprising:

a charge pump with a low voltage terminal, a high voltage terminal, and a clock input;

a voltage divider circuit with a first input coupled to the low voltage terminal, a second input coupled to the high voltage terminal, and an output configured to provide a divided voltage;

a comparator with a first input configured to receive the divided voltage, a second input coupled to the low voltage supply, a reset input, and a comparator output; and

a pulse generator with an input coupled to the comparator output and an output coupled to the reset input and the clock input,

wherein the voltage divider circuit further comprises:

a reference current generator with an input coupled to the low voltage terminal and a reference current generator output;

a current mirror with a current mirror input coupled to the reference current generator output, and a current mirror output; and

a voltage divider with a first terminal coupled to the high voltage terminal, a second terminal coupled to the current mirror output, and an output configured to provide the divided voltage, wherein the voltage divider further comprises:

a first n-type metal oxide semiconductor (NMOS) transistor with a source coupled to the output of the current mirror, a drain, and a gate;

a second NMOS transistor with a source coupled to the drain of the first NMOS transistor, a drain, and a gate coupled to the drain of the second NMOS transistor and to the gate of the first NMOS transistor;

a first PMOS transistor with a drain coupled to the source of the second NMOS transistor, a source, and a gate coupled to the drain of the first PMOS transistor; and

a second PMOS transistor with a source coupled to the high voltage terminal, a drain coupled to the source of the first PMOS transistor, and a gate coupled to the gate of the first PMOS transistor.

17. The integrated circuit of claim 16 , wherein:

the second PMOS transistor has an adjustable voltage threshold (Vth) under control of a first control input; and

the first NMOS transistor has an adjustable Vth under control of a second control input.

18. The integrated circuit of claim 16 , wherein the reference current generator further comprises:

a third NMOS transistor with a source coupled to the current mirror input, a drain, and a gate coupled to the drain of the third NMOS transistor;

a third PMOS transistor with a drain coupled to the source of the first NMOS transistor, a source coupled to the drain of the third NMOS transistor, and a gate coupled to the drain of the third PMOS transistor; and

a fourth PMOS transistor with a source coupled to the low voltage terminal, a drain coupled to the source of the third PMOS transistor, and a gate coupled to the gate of the first PMOS transistor.

19. The integrated circuit of claim 16 , further comprising:

a multiplexer selectively coupling the output of the pulse generator to the input of the charge pump during a sleep mode based on a sleep signal, and selectively coupling a clock signal to the clock input during a wake mode based on the sleep signal.