IP Library Granted Patent US 12,394,692
Granted Patent B2
US 12,394,692 · App. 17/817,736 · Granted Aug 19, 2025

Power circuit module

Inventors: Atapol Prajuckamol (Thanyaburi, TH); Chee Hiong Chew (Seremban, MY); Olaf Zschieschang (Sinsheim, DE)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/4924H01L21/4853H01L21/4875H01L23/3735H01L23/49811H01L23/49844H01L24/40H01L24/48H01L25/072H01L2224/40139H01L2224/40227H01L2224/40247H01L2224/48139H01L2224/48227H01L2224/48247H01L2924/10253H01L2924/10272H01L2924/13055H01L2924/13091
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Quick Facts
Patent No.
US 12,394,692
App. No.
17/817,736
Granted
Aug 19, 2025
Kind
B2
Abstract

A circuit module includes a substrate with a patterned metal surface. The patterned metal surface includes a conductive terminal pad, a first conductive pad, and a second conductive pad that is non-adjacent to the conductive terminal pad. A first circuit portion is assembled on the first conductive pad and a second circuit portion is assembled on the second conductive pad. A conductive bridge electrically couples the conductive terminal pad and the second conductive pad. The conductive bridge includes an elevated span extending above and across the first conductive pad.

Claims (32)

1. A circuit module comprising:

a substrate with a patterned metal surface, the patterned metal surface including a conductive terminal pad, a first conductive pad, and a second conductive pad, the second conductive pad being non-adjacent to the conductive terminal pad;

a first circuit portion assembled on the first conductive pad;

a second circuit portion assembled on the second conductive pad;

a conductive bridge coupled to the conductive terminal pad and the second conductive pad, the conductive bridge including an elevated span extending above and across the first conductive pad, and

at least one first semiconductor device die is disposed with a drain-side down on of the first conductive pad, and at least one second semiconductor device die is disposed with a drain-side down on the second conductive pad.

2. The circuit module of claim 1 , further comprising, a current path from the conductive terminal pad directly to the second conductive pad through the conductive bridge avoiding use of traces around the first conductive pad for current flow.

3. The circuit module of claim 1 , wherein the conductive terminal pad, the first conductive pad, and the second conductive pad are each formed by areas that are bilaterally symmetric about a median axis of the substrate.

4. The circuit module of claim 1 , wherein the conductive bridge is made of a metal or a metal alloy.

5. The circuit module of claim 1 , wherein the at least one first semiconductor device die has source contacts on a top side that are connected to source contacts of a next first semiconductor device die by first wire bonds or a first connector clip and wherein the at least one second semiconductor device die has source contacts on a top side that are connected to source contacts of a next second semiconductor device die by second wire bonds or a second connector clip.

6. The circuit module of claim 5 , wherein the conductive terminal pad is a first conductive terminal pad and wherein the at least one first semiconductor device die has its source contacts connected to a second conductive terminal pad, and the at least one second semiconductor device die has its source contacts connected to the first conductive pad.

7. The circuit module of claim 1 , wherein the conductive terminal pad is a first conductive terminal pad, wherein a source signal pin for the at least one first semiconductor device die is attached to a second conductive terminal pad, and wherein a source signal pin for the at least one second semiconductor device die is attached to the first conductive pad.

8. The circuit module of claim 7 , wherein the at least one first semiconductor device die has its gate contact connected to a third conductive pad disposed on the substrate, and the at least one second semiconductor device die has its gate contact connected to a fourth conductive pad disposed on the substrate.

9. The circuit module of claim 1 , wherein the at least one first semiconductor device die has a gate contact on a top side that is connected to a gate contact of a next first semiconductor device die by a first wire bond, and wherein the at least one second semiconductor device die has a gate contact on a top side that is connected to a gate contact of a next second semiconductor device die by a second wire bond.

10. The circuit module of claim 1 , wherein the substrate is one of a printed circuit board or a direct bonded metal (DBM) substrate.

11. The circuit module of claim 1 configured as a single side directly cooled (SSDC) power module.

12. A circuit module comprising:

a substrate with a patterned metal surface, the patterned metal surface including a conductive terminal pad, a first conductive pad, and a second conductive pad, the second conductive pad being non-adjacent to the conductive terminal pad;

a first circuit portion assembled on the first conductive pad;

a second circuit portion assembled on the second conductive pad;

a conductive bridge coupled to the conductive terminal pad and the second conductive pad, the conductive bridge including an elevated span extending above and across the first conductive pad; and

at least one first semiconductor device die is disposed on the first conductive pad, and at least one second semiconductor device die is disposed on the second conductive pad,

the at least one first semiconductor device die or the at least one second semiconductor device die include at least one of an insulated-gate bipolar transistor (IGBT), a fast recovery diode (FRD), a silicon metal-oxide-semiconductor field effect transistor (silicon MOSFET), and a silicon carbide MOSFET.

13. A power circuit package comprising:

a plurality of conductive pads disposed on a surface of a substrate, the plurality of conductive pads including a conductive terminal pad disposed in an edge portion of the substrate along a top edge of the substrate, a first conductive pad disposed in an upper portion of the substrate next to the edge portion, and a second conductive pad disposed in a lower portion of the substrate next to the upper portion;

a first sub circuit assembled on the first conductive pad, wherein the first sub circuit is a low side driver circuit and includes a low side semiconductor switching device disposed on the first conductive pad;

a second sub circuit assembled on the second conductive pad, wherein the second sub circuit is a high side driver circuit and includes a high side semiconductor switching device disposed on the second conductive pad; and

a conductive bridge coupled to the conductive terminal pad and the second conductive pad, the conductive bridge including a span extending above first conductive pad and the first sub circuit assembled on the first conductive pad.

14. The power circuit package of claim 13 , wherein the second conductive pad is not adjacent to the conductive terminal pad, and the power circuit package further comprises:

a current path from the conductive terminal pad directly to the second conductive pad through the conductive bridge avoiding use of traces around the first conductive pad on the substrate for current flow.

15. The power circuit package of claim 13 , wherein the low side semiconductor switching device and the high side semiconductor switching device include at least one of an insulated-gate bipolar transistor (IGBT), a fast recovery diode (FRD), a silicon metal-oxide-semiconductor field effect transistor (silicon MOSFET), and a silicon carbide MOSFET.

16. The power circuit package of claim 13 , wherein the substrate is direct bonded (DBM) substrate, and the power circuit package is configured as a single side directly cooled (SSDC) power circuit package.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 061879, FRAME 0655 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: FAIRCHILD SEMICONDUCTOR CORPORATION; SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 064123/0001 →
SECURITY INTEREST Recorded Nov 3, 2022
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 061879/0655 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2022
From: PRAJUCKAMOL, ATAPOL; CHEW, CHEE HIONG; ZSCHIESCHANG, OLAF
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 060740/0958 →