Semiconductor device structure
Semiconductor device structures are provided. The semiconductor device structure includes a substrate and a first fin structure protruding from the substrate. The semiconductor device structure further includes an isolation layer formed around the first fin structure and covering a sidewall of the first fin structure and a gate stack formed over the first fin structure and the isolation layer. The semiconductor device structure further includes a first source/drain structure formed over the first fin structure and spaced apart from the gate stack and a contact structure formed over the first source/drain structure. The semiconductor device structure includes a dielectric structure formed through the contact structure. In addition, the contact structure and the dielectric structure has a first slope interface that slopes downwardly from a top surface of the contact structure to a top surface of the isolation layer.
1. A semiconductor device structure, comprising:
a substrate;
a first fin structure protruding from the substrate;
an isolation layer formed around the first fin structure and covering a sidewall of the first fin structure;
a gate stack formed over the first fin structure and the isolation layer;
a first source/drain structure formed over the first fin structure and spaced apart from the gate stack;
a contact structure formed over the first source/drain structure;
a dielectric structure formed through the contact structure; and
a cap layer formed over the contact structure,
wherein the contact structure and the dielectric structure has a first slope interface that slopes downwardly from a top surface of the contact structure to a top surface of the isolation layer, and the contact structure covers the top surface of the isolation layer, and wherein the cap layer and the dielectric structure has a second slope interface that slopes downwardly from a top surface of cap layer to the top surface of the contact structure.
2. The semiconductor device structure as claimed in claim 1 , wherein the dielectric structure physically contacts the top surface of the isolation layer.
3. The semiconductor device structure as claimed in claim 1 , wherein the cap layer vertically overlaps the first source/drain structure and the isolation layer.
4. The semiconductor device structure as claimed in claim 1 , further comprising:
a second fin structure protruding from the substrate; and
a second source/drain structure formed over the second fin structure,
wherein the contact structure continuously extends from the first source/drain structure to the second source/drain structure.
5. The semiconductor device structure as claimed in claim 4 , wherein the dielectric structure and the second source/drain structure are at opposite sides of the first source/drain structure.
6. A semiconductor device structure, comprising:
a substrate;
a fin structure protruding from the substrate and having a first longitudinal axis along a first direction;
a gate stack formed across the fin structure along a second direction different from the first direction;
a source/drain structure attached to the fin structure;
a contact structure formed over the source/drain structure and having a second longitudinal axis along the second direction; and
a dielectric structure formed through the contact structure and having a top surface and a bottom surface, wherein the dielectric structure has a first dimension at the top surface along the second direction and a second dimension at the bottom surface along the second direction, and the first dimension is greater than the second dimension, and the bottom surface of the dielectric structure is no lower than a bottom surface of the contact structure.
7. The semiconductor device structure as claimed in claim 6 , further comprising:
a liner layer laterally sandwiched between the contact structure and the gate stack along the first direction, wherein the liner layer vertically covers the source/drain structure.
8. The semiconductor device structure as claimed in claim 6 , further comprising:
a first cap layer formed over the contact structure, wherein the first cap layer has a third dimension at its top portion along the second direction and a fourth dimension at its bottom portion along the second direction, and the fourth dimension is greater than the third dimension.
9. The semiconductor device structure as claimed in claim 8 , wherein the first cap layer has a fifth dimension at its top portion along the first direction and a sixth dimension at its bottom portion along the first direction, and the fifth dimension is greater than the sixth dimension.
10. The semiconductor device structure as claimed in claim 8 , further comprising:
a second cap layer formed over the gate stack, wherein the second cap layer has a seventh dimension at its top portion along the first direction and an eighth dimension at its bottom portion along the first direction, and the seventh dimension is greater than the eighth dimension.
11. The semiconductor device structure as claimed in claim 10 , wherein the second cap layer is thicker than the first cap layer.
12. The semiconductor device structure as claimed in claim 6 , wherein the bottom surface of the dielectric structure is substantially level with the bottom surface of the contact structure.
13. A semiconductor device structure, comprising:
a fin structure protruding from a substrate and extending along a first direction;
a gate stack formed over the substrate and extending along a second direction different from the first direction;
a dielectric structure spaced apart from the gate stack along the second direction, wherein the dielectric structure has a slope sidewall surface;
source/drain structures formed at opposite sides of the gate stack along the first direction;
a contact structure formed over the source/drain structures and extending along and in contact with a lower portion of the slope sidewall surface of the dielectric structure; and
a first cap layer vertically overlapping the contact structure and extending along and in contact with an upper portion of the slope sidewall surface of the dielectric structure.
14. The semiconductor device structure as claimed in claim 13 , further comprising:
an isolation layer formed around the fin structure,
wherein an end of the slope sidewall surface of the dielectric structure and a bottom surface of the contact structure joins at a top surface of the isolation layer.
15. The semiconductor device structure as claimed in claim 13 , further comprising:
a second cap layer formed over the gate stack,
wherein the first cap layer has a first dimension along a third direction and the second cap layer has a second dimension along the third direction, the third direction is substantially vertical to the first direction and the second direction, and the first dimension is smaller than the second dimension.
16. The semiconductor device structure as claimed in claim 15 , further comprising:
a liner layer sandwiched between the first cap layer and the second cap layer along the first direction, wherein the liner layer is in direct contact with the source/drain structures.
17. The semiconductor device structure as claimed in claim 16 , wherein the liner layer is in direct contact with the dielectric structure.
18. The semiconductor device structure as claimed in claim 16 , further comprising:
a spacer sandwiched between the liner layer and second cap layer along the first direction, wherein a top surface of the second cap layer is higher than a top surface of the spacer.
19. The semiconductor device structure as claimed in claim 14 , wherein an interface between the first cap layer and the dielectric structure and an interface between the source/drain structures and the dielectric structure are both coincident with a first surface.
20. The semiconductor device structure as claimed in claim 1 , wherein the top surface of the cap layer is narrower than the top surface of the contact structure.