IP Library Granted Patent US 11,784,176
Granted Patent B2
US 11,784,176 · App. 17/818,822 · Granted Oct 10, 2023

Light emitting diode device containing a positive photoresist insulating spacer and a conductive sidewall contact and method of making the same

Inventors: Willibrordus Gerardus Maria Van Den Hoek (Saratoga, CA); Tsun Yin Lau (Sunnyvale, CA); Cameron Danesh (Los Altos Hills, CA); Fariba Danesh (Los Altos Hills, CA)
Assignee: NANOSYS, INC.
H01L25/167H01L33/0025H01L33/06H01L33/08H01L33/12H01L33/24H01L33/32H01L33/405H01L33/56H01L33/62H01L2933/005H01L2933/0066
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Quick Facts
Patent No.
US 11,784,176
App. No.
17/818,822
Granted
Oct 10, 2023
Kind
B2
Abstract

A light emitting device includes a backplane, an array of light emitting diodes attached to a frontside of the backplane, a positive tone, imageable dielectric material layer, such as a positive photoresist layer, located on the frontside of the backplane and laterally surrounding the array of light emitting diodes, such that sidewalls of the light emitting diodes contacting the positive tone, imageable dielectric material layer have a respective reentrant vertical cross-sectional profile, and at least one common conductive layer located over the positive tone, imageable dielectric material layer and contacting the light emitting diodes.

Claims (15)

1. A method of forming a light emitting device, comprising:

attaching an array of light emitting diodes to a frontside of a backplane;

applying a positive tone, imageable dielectric material layer to a frontside of the backplane;

vertically recessing the positive tone, imageable dielectric material layer such that a top surface of the positive tone, imageable dielectric material layer is formed below a horizontal plane including top surfaces of the light emitting diodes, wherein sidewalls of the light emitting diodes contacting the positive tone, imageable dielectric material layer have a respective reentrant vertical cross-sectional profile; and

forming a transparent conductive layer over the positive tone, imageable dielectric material layer.

2. The method of claim 1 , wherein:

the positive tone, imageable dielectric material layer comprises a positive photoresist layer; and

sidewalls of the light emitting diodes are reverse-tapered to provide a variable horizontal cross-sectional area that increases with a vertical distance from a frontside surface of the backplane upon attaching the array of light emitting diodes to the frontside of the backplane.

3. The method of claim 2 , wherein vertically recessing the positive photoresist layer comprises performing a blanket exposure process that uncross-links a cross-linked polymer in an upper portion of the positive photoresist layer and subsequently performing a development process.

4. The method of claim 2 , wherein vertically recessing the positive photoresist layer comprises performing a blanket partial ashing process that removes an upper portion of the positive photoresist layer without removing a lower portion of the positive photoresist layer.

5. The method of claim 2 , wherein:

each of the light emitting diodes comprise a respective active region configured to emit light upon application of a bias voltage thereacross;

a matrix portion of the positive photoresist layer adjoining the tapered encirclement portions and continuously extending around each of the light emitting diodes; and

the top surface of the positive photoresist layer is formed between a first horizontal plane including top surfaces of the light emitting diodes and a second horizontal plane including the active regions of the light emitting diodes after vertically recessing the positive photoresist layer.

6. The method of claim 1 , wherein the light emitting diodes comprise a respective n-doped compound semiconductor substrate layer having a horizontal cross-sectional area that strictly increases with a distance from the frontside of the backplane.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2024
From: GLO TECHNOLOGIES LLC
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 068297/0220 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 6, 2023
From: SYSONAN, INC.
To: GLO TECHNOLOGIES LLC
Reel/Frame 065178/0210 →
CHANGE OF NAME Recorded Oct 5, 2023
From: NANOSYS, INC.
To: SYSONAN, INC.
Reel/Frame 065156/0416 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2022
From: VAN DEN HOEK, WILLIBRORDUS GERARDUS MARIA; LAU, TSUN YIN; DANESH, CAMERON; DANESH, FARIBA
To: NANOSYS, INC.,
Reel/Frame 060770/0205 →