Controlling a data processing array using an array controller
An integrated circuit includes a data processing array. The data processing array includes a plurality of compute tiles each having a processor. The integrated circuit includes an array controller coupled to the data processing array. The array controller is adapted to configure the plurality of compute tiles of the data processing array to implement an application. The application specifies kernels executable by the processors and stream channels that convey data to the plurality of compute tiles. The array controller is configured to initiate execution of workloads by the data processing array as configured with the application.
1 . An integrated circuit, comprising:
a data processing array including a plurality of compute tiles each having a processor with program memory, a direct memory access circuit, and a stream switch coupled to other stream switches in adjacent compute tiles; and
an array controller coupled to the data processing array, wherein the array controller is adapted to configure the plurality of compute tiles of the data processing array to implement an application by loading kernels executable by the processors into respective program memories of the plurality of compute tiles and loading configuration data into configuration registers of the stream switches to implement stream channels that convey data to the plurality of compute tiles;
wherein the array controller is configured to initiate execution of workloads by the data processing array by implementing different modes of data movement in the data processing array for different ones of the workloads by, at least in part, programming the direct memory access circuits to convey a number of different feature maps and a number of different weights over the stream channels for distribution to different ones of the plurality of compute tiles for the different modes of data movement, wherein each mode of data movement varies at least one of the number of different feature maps or the number of different weights conveyed.
2 . The integrated circuit of claim 1 , wherein the data processing array further comprises:
a plurality of memory tiles coupled to the plurality of compute tiles, wherein each memory tile includes a random-access memory, a direct memory access circuit coupled to the random-access memory, and a stream switch coupled to the direct memory access circuit and other stream switches in an adjacent compute tile and one or more other memory tiles; and
wherein the array controller further programs direct memory access circuits of the plurality of memory tiles to implement the different modes of data movement.
3 . The integrated circuit of claim 1 , wherein the array controller is configured to, during runtime of the application, provide a runtime parameter to a selected compute tile of the plurality of compute tiles, wherein the runtime parameter specifies a selected random access memory from a plurality of random access memories in which the processor of the selected compute tile, in executing the kernel, stores data.
4 . The integrated circuit of claim 1 , wherein the array controller is configured to, during runtime of the application, provide a runtime parameter to a selected compute tile of the plurality of compute tiles, wherein the runtime parameter specifies a selected random access memory from a plurality of random access memories in which the processor of the selected compute tile, in executing a selected kernel of the kernels, stores data.
5 . The integrated circuit of claim 4 , wherein the array controller is configured to control a number of iterations performed by the plurality of compute tiles to perform each workload.
6 . The integrated circuit of claim 1 , wherein the array controller is configured to, during runtime of the application, provide a runtime parameter to a selected compute tile of the plurality of compute tiles; and
wherein the program memory of the selected compute tile includes a plurality of kernels and the runtime parameter selects a selected kernel of the plurality of kernels for execution.
7 . The integrated circuit of claim 6 , wherein the runtime parameter is specific to a mode of data movement.
8 . The integrated circuit of claim 6 , wherein the runtime parameter selects a kernel of the plurality of kernels to execute on a per layer basis.
9 . The integrated circuit of claim 1 , wherein the array controller is hardwired.
10 . The integrated circuit of claim 1 , wherein the array controller is implemented using programmable logic.
11 . The integrated circuit of claim 1 , wherein:
the data processing array is partitioned into a first partition including a first subset of the plurality of compute tiles and a second partition including a second subset of the plurality of compute tiles;
the array controller is adapted to:
configure the first partition with the application and initiate execution of the workloads of the application;
configure the second partition with a different application and initiate execution of workloads of the different application; and
the first partition operates independently of the second partition.
12 . The integrated circuit of claim 11 , wherein the array controller is configured to sequentially implement a plurality of modes of data movement in each partition over time, wherein the plurality of modes of data movement implemented by the array controller in each partition are specific to the application executed in the partition.
13 . An integrated circuit, comprising:
a data processing array including a plurality of compute tiles each having a processor, a direct memory access circuit, and a stream switch coupled to other stream switches in adjacent compute tiles, wherein the data processing array is subdivided into a first partition including a first subset of the plurality of compute tiles and a second partition including a second subset of the plurality of compute tiles;
a first array controller adapted to configure the first partition to implement a first application, wherein the first application specifies kernels executable by the processors of the first partition and first stream channels implemented by the stream switches that convey data to the first subset of the plurality of compute tiles of the first partition; and
a second array controller adapted to configure the second partition to implement a second application, wherein the second application specifies kernels executable by the processors of the second partition and second stream channels implemented by the stream switches that convey data to the second subset of the plurality of compute tiles of the second partition;
wherein the first array controller and the second array controller each is configured to initiate execution of workloads in the respective partitions by implementing different modes of data movement in the respective partitions for different ones of the workloads by, at least in part,
programming the direct memory access circuits of the plurality of compute tiles of the respective partitions to convey a number of different feature maps and a number of different weights over the stream channels for distribution to different ones of the plurality of compute tiles for the different modes of data movement, wherein each mode of data movement varies at least one of the number of different feature maps or the number of different weights conveyed.
14 . The integrated circuit of claim 13 , wherein the first partition operates independently of the second partition.
15 . The integrated circuit of claim 13 , wherein the first array controller and the second array controller are hardwired.
16 . The integrated circuit of claim 13 , wherein the first array controller and the second array controller are implemented in programmable logic.
17 . The integrated circuit of claim 13 , wherein the first array controller is hardwired and the second array controller is implemented using programmable logic.
18 . The integrated circuit of claim 13 , wherein:
the first array controller is configured to, during runtime of the first application, sequentially implement a plurality of modes of data movement in the first partition over time to perform a workload for the first application; and
the second array controller is configured to, during runtime of the second application, sequentially implement a plurality of modes of data movement in the second partition over time to perform a workload for the second application.
19 . The integrated circuit of claim 13 , wherein:
the first array controller is configured to, during runtime of the first application, provide a first runtime parameter to a selected compute tile of the first partition, wherein the first runtime parameter configures an operational parameter of a kernel executed by the selected compute tile of the first partition; and
the second array controller is configured to, during runtime of the second application, provide a second runtime parameter to a selected compute tile of the second partition, wherein the second runtime parameter configures an operational parameter of a kernel executed by the selected compute tile of the second partition.
20 . The integrated circuit of claim 19 , wherein each runtime parameter is specific to a mode of data movement and specifies a dimension of a particular layer of the respective application.