Memory system

1. A memory system comprising:

a nonvolatile memory that includes a plurality of blocks, each of the plurality of blocks being a unit of a data erase operation and including a plurality of storage locations, each of the plurality of storage locations including a plurality of memory cells; and

a controller electrically connected to the nonvolatile memory and configured to execute a data write operation on a write destination block among the plurality of blocks by using a multi-step program operation that includes at least a first step program operation and a second step program operation, wherein

the controller is configured to execute the data write operation on the plurality of storage locations of the write destination block in an order in which:

the first step program operation on a first storage location of the write destination block is executed;

after completion of the first step program operation on the first storage location, the first step program operation on a second storage location of the write destination block is executed;

in response to completion of the first step program operation on the second storage location, the second step program operation on the first storage location is executed; and

after completion of the second step program operation on the first storage location, the first step program operation on a third storage location of the write destination block is executed, wherein

the controller is further configured to,

in response to resuming of power supply to the memory system after shutoff of power supply to the memory system:

identify, in a first block among the plurality of blocks, a fourth storage location on which the second step program operation is executed last among the plurality of storage locations of the first block according to the order;

determine whether a first condition that (A) a fifth storage location of the first block stores unreadable data and (B) each of the plurality of memory cells of a sixth storage location of the first block has a threshold voltage that corresponds to an erased state, is satisfied, wherein,

among the plurality of storage locations of the first block, according to the order,

the first step program operation on the fourth storage location has been executed;

after completion of the first step program operation on the fourth storage location, the first step program operation on the fifth storage location has been executed;

in response to completion of the first step program operation on the fifth storage location, the second step program operation on the fourth storage location has been executed; and

the first step program operation on the sixth storage location is to be executed after completion of the second step program operation on the fourth storage location; and

when the first condition is satisfied, determine the sixth storage location of the first block as a next write destination storage location.

2. The memory system according to claim 1 , wherein

the controller is further configured to,

when the first condition is not satisfied:

manage the first block as an unavailable block;

allocate a second block among the plurality of blocks as a new write destination block; and

determine a head storage location of the plurality of storage locations of the second block, as the next write destination storage location.

3. The memory system according to claim 1 , wherein

the plurality of blocks each include a plurality of word lines which each connect at least one of the plurality of the storage locations,

the controller is further configured to, when the first storage location and the second storage location are connected to a head word line of the write destination block:

wait until at least first data to be written to the first storage location and second data to be written to the second storage location are prepared;

upon the first data and the second data having been prepared, execute the first step program operation for the first data on the first storage location and the first step program operation for the second data on the second storage location; and

upon at least the first step program operation for the second data on the second storage location having been completed, execute the second step program operation for the first data on the first storage location.

4. The memory system according to claim 1 , wherein

the controller is further configured to,

upon resuming of power supply to the memory system after power supply to the memory system is shut off by unexpected power loss:

identify the fourth storage location of the first block;

determine whether the first condition is satisfied; and

when the first condition is satisfied, determine the sixth storage location of the first block as the next write destination storage location.

5. The memory system according to claim 1 , wherein

the controller is further configured to:

store write destination information about a write destination storage location to the nonvolatile memory; and

upon resuming of power supply to the memory system after shutoff of power supply to the memory system,

identify the fourth storage location by reading data from one or more of the plurality of storage locations of the first block from a last storage location of the first block indicated by the write destination information.

6. The memory system according to claim 1 , wherein

the first step program operation makes a threshold voltage of at least one of the plurality of memory cells of a write destination storage location higher than a threshold voltage that corresponds to the erased state,

but data written to the write destination storage location is unreadable after completion of the first step operation,

the second step program operation adjusts the threshold voltage of the at least one of the plurality of memory cells of the write destination storage location, and

data written to the write destination storage location becomes readable after completion of the second step program operation.