Synchronous rectification control in LLC topology
Systems for power conversion, and controllers and methods for operating a power converter. The method includes receiving high-side and low-side primary signals that drive primary transistors of a power converter. The method also includes receiving a combined drain voltage signal for high-side and low-side synchronous rectifier (SR) transistors of the power converter. The method further includes generating a high-side SR signal based on the low-side primary signal and generating a low-side SR signal based on the high-side primary signal. The method also includes determining high-side and low-side body diode conduction times based on the combined drain voltage signal. The method further includes adjusting the high-side SR signal based on the high-side body diode conduction time and adjusting the low-side SR signal based on the low-side body diode conduction time.
1. A method for operating a power converter, the method comprising:
receiving a high-side primary signal that drives a high-side primary transistor of a first stage of the power converter;
receiving a low-side primary signal that drives a low-side primary transistor of the first stage;
generating a combined drain voltage signal by adding:
a drain voltage signal of a high-side synchronous rectifier (SR) transistor of a second stage of the power converter, and
a drain voltage signal of a low-side SR transistor of the second stage of the power converter;
generating, based on the low-side primary signal, a high-side SR signal that drives the high-side SR transistor;
determining a high-side body diode conduction time of a high-side body diode of the second stage based on the combined drain voltage signal;
generating, based on the high-side primary signal, a low-side SR signal that drives the low-side SR transistor;
determining a low-side body diode conduction time of a low-side body diode of the second stage based on the combined drain voltage signal;
adjusting the high-side SR signal based on the high-side body diode conduction time; and
adjusting the low-side SR signal based on the low-side body diode conduction time.
2. The method of claim 1 , wherein adjusting the high-side SR signal based on the high-side body diode conduction time further includes:
adjusting the high-side SR signal to increase a conduction cycle of the high-side SR transistor when the high-side body diode conduction time is greater than a predetermined conduction time, and
adjusting the high-side SR signal to decrease the conduction cycle of the high-side SR transistor when the high-side body diode conduction time is less than the predetermined conduction time.
3. The method of claim 2 , wherein generating the high-side SR signal further includes:
generating the high-side SR signal to turn on the high-side SR transistor when the low-side primary signal indicates that the low-side primary transistor is turned on, and
generating the high-side SR signal to turn off the high-side SR transistor at an end of the conduction cycle.
4. The method of claim 1 , wherein determining the high-side body diode conduction time based on the combined drain voltage signal further comprising:
generating a comparison signal by comparing the combined drain voltage signal to a reference voltage, and
determining the high-side body diode conduction time as a duration between the high-side SR transistor being turned off and a transition of the comparison signal.
5. The method of claim 1 , wherein generating the high-side SR signal further includes:
generating a comparison signal by comparing the combined drain voltage signal to a reference voltage, and
generating the high-side SR signal to turn on the high-side SR transistor responsive to a transition of the comparison signal after the low-side SR transistor is turned off.
6. The method of claim 5 , further including ignoring the comparison signal during a predetermined period of time following the low-side SR transistor being turned off.
7. The method of claim 5 , wherein generating the high-side SR signal further includes generating the high-side SR signal to turn on the high-side SR transistor after a predetermined period of time following the low-side primary signal indicating that the low-side primary transistor is turned on.
8. The method of claim 1 , wherein generating the high-side SR signal further includes generating the high-side SR signal to turn off the high-side SR transistor after a period of time following the low-side primary signal indicating that the low-side primary transistor is turned off, and
wherein adjusting the high-side SR signal based on the high-side body diode conduction time further includes increasing the period of time when the high-side body diode conduction time is greater than a predetermined conduction time.
9. A system for power conversion, comprising:
a power converter including:
a first stage having:
a high-side primary transistor driven by a high-side primary signal, and
a low-side primary transistor driven by a low-side primary signal, and
a second stage having a high-side synchronous rectifier (SR) transistor, a high-side body diode, a low-side SR transistor, and a low-side body diode; and
a controller configured to:
generate a combined drain voltage signal by adding a drain voltage signal of the high-side SR transistor and a drain voltage signal of the low-side SR transistor,
generate, based on the low-side primary signal, a high-side SR signal that drives the high-side SR transistor,
determine a high-side body diode conduction time of the high-side body diode based on the combined drain voltage signal for the high-side SR transistor and the low-side SR transistor,
generate, based on the high-side primary signal, a low-side SR signal that drives the low-side SR transistor,
determine a low-side body diode conduction time of the low-side body diode based on the combined drain voltage signal,
adjust the high-side SR signal based on the high-side body diode conduction time, and
adjust the low-side SR signal based on the low-side body diode conduction time.
10. The system of claim 9 , wherein, to adjust the high-side SR signal based on the high-side body diode conduction time, the controller is further configured to:
adjust the high-side SR signal to increase a conduction cycle of the high-side SR transistor when the high-side body diode conduction time is greater than a predetermined conduction time, and
adjust the high-side SR signal to decrease the conduction cycle of the high-side SR transistor when the high-side body diode conduction time is less than the predetermined conduction time.
11. The system of claim 10 , wherein, to generate the high-side SR signal, the controller is further configured to:
generate the high-side SR signal to turn on the high-side SR transistor when the low-side primary signal indicates that the low-side primary transistor is turned on, and
generate the high-side SR signal to turn off the high-side SR transistor at an end of the conduction cycle.
12. The system of claim 9 , wherein the controller further includes a comparator configured to generate a comparison signal by comparing the combined drain voltage signal to a reference voltage, and
wherein, to determine the high-side body diode conduction time based on the combined drain voltage signal, the controller is further configured to determine the high-side body diode conduction time as a duration between the high-side SR transistor being turned off and a transition of the comparison signal.
13. The system of claim 9 , wherein the controller further includes a comparator configured to generate a comparison signal by comparing the combined drain voltage signal to a reference voltage, and
wherein, to generate the high-side SR signal, the controller is further configured to generate the high-side SR signal to turn on the high-side SR transistor responsive to a transition of the comparison signal after the low-side SR transistor is turned off.
14. The system of claim 13 , wherein the controller is further configured to ignore the comparison signal during a predetermined period of time following the low-side SR transistor being turned off.
15. The system of claim 13 , wherein, to generate the high-side SR signal, the controller is further configured to generate the high-side SR signal to turn on the high-side SR transistor after a predetermined period of time following the low-side primary signal indicating that the low-side primary transistor is turned on.
16. The system of claim 9 , wherein, to generate the high-side SR signal, the controller is further configured to generate the high-side SR signal to turn off the high-side SR transistor after a period of time following the low-side primary signal being turned off, and
wherein, to adjust the high-side SR signal based on the high-side body diode conduction time, the controller is further configured to increase the period of time when the high-side body diode conduction time is greater than a predetermined conduction time.
17. The system of claim 9 , wherein the controller further includes:
a comparator configured to generate a comparison signal by comparing the combined drain voltage signal to a reference voltage, and
a pair of diodes configured to generate the combined drain voltage signal by adding the drain voltage signal of the high-side SR transistor and the drain voltage signal of the low-side SR transistor, wherein an anode of each of the pair of diodes is coupled to a non-inverting input of the comparator,
wherein, to determine the high-side body diode conduction time based on the combined drain voltage signal, the controller is further configured to determine the high-side body diode conduction time based on the comparison signal.
18. A controller for a power converter, comprising:
a first reference terminal configured to receive a high-side primary signal that drives a high-side primary transistor of a first stage of the power converter;
a second reference terminal configured to receive a low-side primary signal that drives a low-side primary transistor of the first stage;
a node for generating a combined drain voltage signal by adding:
a drain voltage signal of a high-side synchronous rectifier (SR) transistor of a second stage of the power converter, and
a drain voltage signal of a low-side SR transistor of the second stage of the power converter; and
an SR controller configured to:
generate, based on the low-side primary signal, a high-side SR signal that drives the high-side SR transistor,
determine a high-side body diode conduction time of a high-side body diode of the second stage based on the combined drain voltage signal,
generate, based on the high-side primary signal, a low-side SR signal that drives the low-side SR transistor,
determine a low-side body diode conduction time of a low-side body diode of the second stage based on the combined drain voltage signal,
adjust the high-side SR signal based on the high-side body diode conduction time, and
adjust the low-side SR signal based on the low-side body diode conduction time.
19. The controller of claim 18 , wherein, to adjust the high-side SR signal based on the high-side body diode conduction time, the controller is further configured to:
adjust the high-side SR signal to increase a conduction cycle of the high-side SR transistor when the high-side body diode conduction time is greater than a predetermined conduction time, and
adjust the high-side SR signal to decrease the conduction cycle of the high-side SR transistor when the high-side body diode conduction time is less than the predetermined conduction time.
20. The controller of claim 18 , wherein, to determine the high-side conduction body diode time based on the combined drain voltage signal, the controller is further configured to:
generate a comparison signal by comparing the combined drain voltage signal to a reference voltage, and
determine the high-side body diode conduction time as a duration between the high-side SR transistor being turned off and a transition of the comparison signal.